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[VHDL-FPGA-Verilog] booth_mul DL : 0: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Date : 2025-12-19 Size : 19kb User : 李鹏
[VHDL-FPGA-Verilog] S7_UART DL : 0: 利用FPGA实现串口通信，很好的学习资料尤其是对 verilog不熟的朋友-FPGA realization of the use of serial communications, a very good learning materials especially in the wake of a friend Verilog
Date : 2025-12-19 Size : 458kb User : 杜菲
[VHDL-FPGA-Verilog] add_tree_mult DL : 0: 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
Date : 2025-12-19 Size : 1kb User : 江浩
[VHDL-FPGA-Verilog] mulbinarytree DL : 1: 16位二叉树乘法器（阵列乘法器），VHDL实现-16-bit binary tree multiplier (array multiplier), VHDL realization
Date : 2025-12-19 Size : 1.04mb User : jiajunxian
[VHDL-FPGA-Verilog] binary DL : 0: this is for low power dsp for wireless nodes (binary tree computation)
Date : 2025-12-19 Size : 2kb User : kirubadoni
[VHDL-FPGA-Verilog] binarytree DL : 0: Binary tree in system verilog using classes, and automatic function
Date : 2025-12-19 Size : 1kb User : Sam