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[VHDL-FPGA-Verilog] PS2_LCD DL : 0: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.
Date : 2025-12-22 Size : 589kb User : bayernb
[VHDL-FPGA-Verilog] vcpwmcpldcar DL : 0: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码-vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code
Date : 2025-12-22 Size : 937kb User : hxf
[VHDL-FPGA-Verilog] keyboardScan DL : 0: PS2接口键盘扫描码截取电路，VHDL程序。该程序能够捕获PS2键盘按下的按键值，并将其扫描码转换成ASCII码。-PS2 keyboard scan code interception interface circuit, VHDL procedures. The program can capture PS2 keyboard press the keys values and scan codes into ASCII code.
Date : 2025-12-22 Size : 1kb User : 宁新
[VHDL-FPGA-Verilog] ps2_keyboard DL : 0: ps2 keyboard verilog源代码,支持ascii码.扫描码输出,扩展键输出,按下及释放信息输出-ps2 keyboard verilog source code, to support the ascii code. scan code output, the expansion of key output, press and release the information output
Date : 2025-12-22 Size : 5kb User : 李志刚
[VHDL-FPGA-Verilog] PS2_LCD DL : 0: ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符
Date : 2025-12-22 Size : 336kb User : 张海风
[VHDL-FPGA-Verilog] vga_display DL : 0: VGA controller源码及显示汉字和ascii字符的c代码实例，已在DE2-70上实现-vga_controller source code and c code which can display chinese charactors and ASCII code on the VGA
Date : 2025-12-22 Size : 297kb User :
[VHDL-FPGA-Verilog] Rs232sourcecode DL : 0: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Date : 2025-12-22 Size : 5kb User : Ikki
[VHDL-FPGA-Verilog] vhdl DL : 0: ps2 vhdl 实现键盘输入数码管显示ascii码-ps2 vhdl
Date : 2025-12-22 Size : 183kb User : 建宁
[VHDL-FPGA-Verilog] choosebcd DL : 0: 基于vhdl的BCD码转ASCII码的设计，已经经过调试，可直接使用-Vhdl code based on the BCD to ASCII code of the design, debugging has been directly used
Date : 2025-12-22 Size : 1kb User : 郭帅
[VHDL-FPGA-Verilog] ps2 DL : 0: 采用sopc技术，nios2ide开发环境，实现nios对ps2键盘的控制，按键讲ascii码显示在led上-Using sopc technology, nios2ide development environment to achieve nios right ps2 keyboard control, key speakers led the ascii code is displayed in
Date : 2025-12-22 Size : 7.78mb User : 蹇清平
[VHDL-FPGA-Verilog] Visio-schemat_blokowy_niezawodno____ DL : 0: ps2 keyboard verilog source code, to support the ascii code. scan code output, the expansion of key output, press and release the information output
Date : 2025-12-22 Size : 38kb User : Mat
[VHDL-FPGA-Verilog] statemechine DL : 0: We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine from the test bench. Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii. -We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine from the test bench. Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii.
Date : 2025-12-22 Size : 1kb User : dhanagopal
[VHDL-FPGA-Verilog] PS2xianshi DL : 0: FPGA设计简单通信协议的方法。了解PS2的工作原理，扫描码的ASCII码的转换。 -FPGA design of a simple communication protocol method. Learn PS2 works, scan code ASCII code conversions.
Date : 2025-12-22 Size : 417kb User : huangdeyi
[VHDL-FPGA-Verilog] S7_PS2_LCD DL : 0: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s can input characters lcd display 3, in which key on the keyboard is used to clear screen backspce 4, when the lcd display full of character, Press the button in the screen automatically clear from the first line.
Date : 2025-12-22 Size : 641kb User : shi
[VHDL-FPGA-Verilog] rs232_20M_19200 DL : 0: 这是一个串口 vhdl 程序主要完成了他的收发ASCII文本的功能-this is a vhdl serial port program
Date : 2025-12-22 Size : 221kb User : qinjian
[VHDL-FPGA-Verilog] S7_PS2_LCD DL : 0: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait for 1s in the input character lcd display 3, in which key on the keyboard is used to clear the screen backspce 4, when the lcd display full of character, automatically clear the screen press the button, from the first line.
Date : 2025-12-22 Size : 838kb User : 陈亮
[VHDL-FPGA-Verilog] serial DL : 0: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步. 程序的基本工作过程是，按动一个按键SW0，控制器向PC的串口发送“welcome"， PC机接收后显示验证数据是否正确（串口调试工具设成按ASCII码接受方式）. PC可随时向CPLD发送0-F的十六进制数据，CPLD接受后显示在7段数码管上.-The module s function is to verify the implementation and the basic PC, the serial communication function. Need PC, Install a serial debugging tools to verify the functionality of the program. Program implements a receive a 10 bit (ie no parity bit) of the serial controllers, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial Porter law defined by the program parameters div_par decision can change the parameters of the corresponding Baud rate. Program the value of the current set div_par Is 0x104, the corresponding baud rate is 9600. 8 times the baud rate with a clock will be sent or received per A bit of the cycle time is divided into eight time slots in order to pass Information synchronization. The basic process is the work program, press a button SW0, the controller s serial port to the PC "Welcome", PC, after receiving the authentication data displayed is correct (serial debugging tool ASCII code set by the r
Date : 2025-12-22 Size : 2kb User : riversky
[VHDL-FPGA-Verilog] PS2UART_verilog DL : 0: 基于Verilog的PS/2键盘接口实现,接收PS/2键盘数据，并转换成ASCII码，通过RS232发送到PC显示。-Based on Verilog, PS/2 keyboard interface, the receiving PS/2 keyboard data and convert it into ASCII code sent to the PC through the RS232 display.
Date : 2025-12-22 Size : 326kb User : liuxingxing
[VHDL-FPGA-Verilog] S9_PS2_LCD DL : 0: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait for 1s in the input character lcd display 3, in which key on the keyboard is used to clear the screen backspce 4, when the lcd display full of character, automatically clear the screen press the button, from the first line.
Date : 2025-12-22 Size : 9kb User : 袁方
[VHDL-FPGA-Verilog] S7_PS2_LCD DL : 0: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait for 1s in the input character lcd display 3, in which key on the keyboard is used to clear the screen backspce 4, when the lcd display full of character, automatically clear the screen press the button, from the first line.
Date : 2025-12-22 Size : 135kb User : 成语

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