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[VHDL-FPGA-Verilog] AES加密的VHDL源码 DL : 2: 用VHDL语言实现的AES加密算法的源代码，已经在硬件上下载运行实现了。
Date : 2010-11-24 Size : 9.88kb User : zhaojing.w@gmail.com
[VHDL-FPGA-Verilog] AEScoremodules DL : 0: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Date : 2025-12-16 Size : 10kb User : 许茹芸
[VHDL-FPGA-Verilog] aes DL : 0: vhdl implementation of the AES encryption algorithm
Date : 2025-12-16 Size : 239kb User : hesham
[VHDL-FPGA-Verilog] aes DL : 0: 实现了AES在赛灵思器件上的加密程序我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
Date : 2025-12-16 Size : 4kb User : wangrui
[VHDL-FPGA-Verilog] aes DL : 0: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Date : 2025-12-16 Size : 85kb User : dinxj
[VHDL-FPGA-Verilog] AES! DL : 0: AES algorithm very good code tested in xilinx ise tool
Date : 2025-12-16 Size : 9kb User : hr
[VHDL-FPGA-Verilog] aes DL : 0: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Date : 2025-12-16 Size : 2.84mb User : cong
[VHDL-FPGA-Verilog] AES DL : 0: AES implementation in VHDL@!
Date : 2025-12-16 Size : 509kb User : manishrb
[VHDL-FPGA-Verilog] aes DL : 0: verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
Date : 2025-12-16 Size : 7kb User : xie
[VHDL-FPGA-Verilog] aes-core DL : 0: Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
Date : 2025-12-16 Size : 86kb User : fujiwei
[VHDL-FPGA-Verilog] AES DL : 0: FPGA Implementation of AES Encryption and Decryption
Date : 2025-12-16 Size : 1.97mb User : lrx
[VHDL-FPGA-Verilog] aes-vhdl DL : 0: 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
Date : 2025-12-16 Size : 7kb User : Bruce Lee
[VHDL-FPGA-Verilog] AES DL : 0: 利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性-The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching.
Date : 2025-12-16 Size : 8.58mb User : 林涛
[VHDL-FPGA-Verilog] aes-vhdl DL : 0: this file contains vhdl code for aes
Date : 2025-12-16 Size : 117kb User : baby
[VHDL-FPGA-Verilog] aes DL : 0: AES FPGA verilogHDL实现(AES hardware implementation)
Date : 2025-12-16 Size : 36kb User : 猪在飞
[VHDL-FPGA-Verilog] AES 128 ECB Decryption DL : 0: Block mode related AES-EBC Encryption
Date : 2025-12-16 Size : 23kb User : RsD
[VHDL-FPGA-Verilog] AES 128 ECB Encryption DL : 0: Block mode related AES-EBC Decryption
Date : 2025-12-16 Size : 25kb User : RsD
[VHDL-FPGA-Verilog] Package for AES-128 DL : 0: Block mode related AES Package
Date : 2025-12-16 Size : 22kb User : RsD
[VHDL-FPGA-Verilog] aes-master DL : 0: aes master by vhdl code and decode
Date : 2025-12-16 Size : 67kb User : Nguyen Nam
[VHDL-FPGA-Verilog] aes-project-master DL : 0: aes project vhdl FPGA
Date : 2025-12-16 Size : 1.05mb User : Nguyen Nam

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