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[VHDL-FPGA-Verilog] vhdl1 DL : 0: 设计一个四路数据选择器,其功能是将四组不同的数据按要求选择一个输出.输出的那组数据有两个控制信号决定,其真值表如下: 数据选择控制端输出的数据 Input0 Input1 output 0 0 output0 0 1 output1 1 0 output 2 1 1 output 3- Designs four ways according to the selector, its function is chooses four groups of different data according to the request an output Output that group of data has two controls signals to decide, its truth table as follows: Data access control end output data Input0 Input1 output 0 0 output0 0 1 output1 1 0 output 21 1 output 3
Date : 2025-12-21 Size : 27kb User : 晨曦
[VHDL-FPGA-Verilog] 数据结构c描述习题集答案 DL : 0: 减1计数器一、设计要求用Verilog HDL语言设计一个计数器。要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。二、设计原理输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Date : 2025-12-21 Size : 109kb User : tutu
[VHDL-FPGA-Verilog] quartus II中文用户教程(英文版的完全翻译） DL : 0: quartus II中文用户教程(英文版的完全翻译）,和一切爱好可编程器件的同仁共勉之-Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi
Date : 2025-12-21 Size : 825kb User : 田晶昌
[VHDL-FPGA-Verilog] Modelsim中文教程 DL : 0: Modelsim中文教程,有３篇讲Modelsim的资料，对新手是个很好的参考资料-Modelsim Chinese guide, a three stresses Modelsim information, the rookie is a very good reference!
Date : 2025-12-21 Size : 948kb User : 温暖感
[VHDL-FPGA-Verilog] ModelSim_SE_6.1bkey DL : 0: ModelSim SE 6.1 (电子仿真)具体破解-ModelSim SE 6.1 (electronic simulation) Specific crack
Date : 2025-12-21 Size : 223kb User : 卢峰
[VHDL-FPGA-Verilog] CK20-VHDL DL : 0: 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
Date : 2025-12-21 Size : 4kb User : 林海
[VHDL-FPGA-Verilog] ModelSim.SE.v6.0a_keygen DL : 0: ModelSim分析设计教程\ModelSim.SE.v6.0许可生成器，生成license文件-ModelSim Analysis and Design Guide \ ModelSim.SE.v6.0 permission generator , document generation license
Date : 2025-12-21 Size : 215kb User : 袁汇
[VHDL-FPGA-Verilog] DspBuilder6.0_License DL : 0: DspBulider6.0的license破解-DspBulider6.0
Date : 2025-12-21 Size : 456kb User : li
[VHDL-FPGA-Verilog] 6-portRegisterFile DL : 0: 6端口寄存器IP内核VHDL源代码，所需的开发环境是QUARTUS II 6.0。-6-port register IP core VHDL source code, required for the development environment is QUARTUS II 6.0.
Date : 2025-12-21 Size : 28kb User : 周华茂
[VHDL-FPGA-Verilog] quartus6.0 DL : 0: Atlera 公司的开发软件平台quartus 6.0的license-Atlera company quartus 6.0 to develop the software platform of the license
Date : 2025-12-21 Size : 2kb User : guobo
[VHDL-FPGA-Verilog] modelsim6_0_user_guide DL : 0: Modelsim 6.0 中文版使用教程，从安装到使用，图文详解介绍，适合初学者学习-Modelsim 6.0 Chinese version of the use of tutorials, from installation to use, including picture introduction, suitable for beginners to learn
Date : 2025-12-21 Size : 379kb User : 张永杰
[VHDL-FPGA-Verilog] eetop.cn_Altera6.0_10.0sp1 DL : 0: eetop.cn_Altera破解器6.0-10.0sp1.rar包括最新的Quartus10.0破解版。-eetop.cn_Altera cracker 6.0-10.0sp1.rar including the latest Quartus10.0 cracked version.
Date : 2025-12-21 Size : 391kb User : lijiang
[VHDL-FPGA-Verilog] EDAmusicplayer DL : 0: EDA乐曲播放器,在EDA开发工具Quartus II 6.0平台上，采用VHDL语言层次化和模块化的设计方法，通过音符编码的设计思想，预先定制乐曲，实现动态显示乐曲演奏电路的设计-EDA music player
Date : 2025-12-21 Size : 114kb User : 维吉尔
[VHDL-FPGA-Verilog] eetop.cn_Crack_Modelsim.SE.6.6 DL : 0: Modelsim 6.6c keygen
Date : 2025-04-30 Size : 652kb User : 王京
[VHDL-FPGA-Verilog] modelsim-6.0 DL : 0: 硬件描述语言仿真工具modelsim 6.0的附图详细教程-the detail tutorial of modelsim 6.0 with pictures
Date : 2025-12-21 Size : 320kb User : 马腾宇
[VHDL-FPGA-Verilog] Modelsim-6.0-- DL : 0: Modelsim 6.0 詳細教學使用手冊-Of Modelsim 6.0 for more detailed teaching manual
Date : 2025-12-21 Size : 379kb User : 張小唯
[VHDL-FPGA-Verilog] FPGA_USB2.0设计 DL : 0: 把FX2配置成从FIFO的模式，配置为单片机工作时钟24M，端点2输出，字节1024，端点6输入，字节1024，信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟，也就是让FX2给我们的设计当做时钟源，输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input, byte 1024, signal all set to low level and so on. Our module drive clock is configured as an internal output clock, that is, let FX2 give our design as the clock source, and output a clock with the largest configuration clock 48M.)
Date : 2025-12-21 Size : 420kb User : 硅渣渣
[VHDL-FPGA-Verilog] Quartus II 6.0 Handbook DL : 0: Altera's Quartus II 6.0 Handbook
Date : 2022-08-30 Size : 25.51mb User : alz4062
[VHDL-FPGA-Verilog] Anvyl LED Runner DL : 0: This code runs the leds on the Anvyl development board Spartan 6
Date : 2023-02-03 Size : 1.58kb User : umarshahbaz@gmail.com
[VHDL-FPGA-Verilog] Divider-vhdl DL : 1: Divider-VHDL by spartan 6
Date : 2023-12-23 Size : 15.75kb User : dornabit

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