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[VHDL-FPGA-Verilog] HDB3_coder DL : 0: 实现了将64K低速NRZ码复接成2.048M高速HDB3码及其解复接过程，同时还用同步状态机剔除假同步和假失步的状态 -Achieved the 64K low-speed NRZ code 2.048M into high-speed multiplexing and demultiplexing HDB3 code then the process also removed using false synchronous state machine synchronization and false out-of-step state
Date : 2026-01-10 Size : 3mb User : 陈涛
[VHDL-FPGA-Verilog] exer2 DL : 0: 给定一个频率为33MHz的时钟，试利用该时钟得到一个基本均匀的2.048MHz时钟-Given a frequency of 33MHz clock, try to use the clock to get a basic uniform of the 2.048MHz clock
Date : 2026-01-10 Size : 27kb User : 林涛
[VHDL-FPGA-Verilog] gen_nx64k DL : 0: N×64K数控分频模块，可将2.048M时钟分频为一个NX64k的时钟，在E1复用设备上应用。 -N × 64K NC frequency module can be 2.048M NX64k clock frequency for a clock, the E1 multiplexing equipment apply.
Date : 2026-01-10 Size : 1kb User : hq
[VHDL-FPGA-Verilog] hdbn DL : 0: This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703. Note: HDB2 and B3ZS are different names for the same encoding. HDB3 is typically used to encode data at 2.048 (E1), 8.448 (E2) and 34.368Mb/s (E3) B3ZS is typically used to encode data at 44.736Mb/s (T3)
Date : 2026-01-10 Size : 9kb User : fronders