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[VHDL-FPGA-Verilog] tcm_decode DL : 0: TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!
Date : 2025-12-21 Size : 19kb User : 刘超
[VHDL-FPGA-Verilog] FPGAExample DL : 0: 很好的几个FPGA工程，对提高FPGA设计有一定的帮助（注：代码为Verilog编写）。-Several FPGA good works, to improve the FPGA design is certainly helpful to them (Note: The code for the Verilog preparation).
Date : 2025-12-21 Size : 1.09mb User : Phirix Shaw
[VHDL-FPGA-Verilog] LED2 DL : 0: 采用Verilog hdl编程语言实现led显示，有工程代码用QII软件编译调试-led Verilog hdl
Date : 2025-12-21 Size : 110kb User : zhangyanshuang
[VHDL-FPGA-Verilog] FPEGVHDL DL : 0: 这是本人在学FPEG/VHDL快速工程实践入门与提高一书时所写的相关代码。可是本人辛苦整理出来的啊。希望对大家有帮助了-This is my study at FPEG/VHDL Express entry and improve engineering practice when the book written by one of the relevant code. However hard I organize out ah. Hope to have helped the U.S. ... ...
Date : 2025-12-21 Size : 3kb User : Zachary
[VHDL-FPGA-Verilog] C20_sram_vga DL : 0: VGA的FPGA试验工程代码。学习vga的可赶紧下-VGA demo
Date : 2025-12-21 Size : 9.91mb User : arens
[VHDL-FPGA-Verilog] crc DL : 0: 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Date : 2025-12-21 Size : 426kb User : 虎
[VHDL-FPGA-Verilog] PWM_moto_ctrl DL : 0: verilog 代码实现直流电机PWM控制内有整个完整工程和modelsim仿真文件-verilog code for PWM DC motor control to achieve within the whole integrity of engineering and modelsim simulation files
Date : 2025-12-21 Size : 927kb User : 文一左
[VHDL-FPGA-Verilog] sipo8 DL : 0: 串入并出源代码，可进行8位数据的串/并转换。其中包括QUARTUS2的完整工程，有正确的仿真波形供参考。-In series and the source code, can be 8-bit data series/parallel conversion. Including QUARTUS2 complete project,and the correct simulation waveform for reference.
Date : 2025-12-21 Size : 212kb User : simulin_2008
[VHDL-FPGA-Verilog] CameraDemo_Toshiba_800x480_v1 DL : 0: 实时视频采集与再现 actel fpga 工程代码，很有参考价值。-camera demo project
Date : 2025-12-21 Size : 1.9mb User : 丛清
[VHDL-FPGA-Verilog] xyy DL : 0: 基于FPGA的vhdl语言的波形发生器材料及工程代码-FPGA VHDL language-based waveform generator materials and engineering code
Date : 2025-12-21 Size : 6.28mb User : panjun
[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights DL : 0: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Date : 2025-12-21 Size : 285kb User : shujian
[VHDL-FPGA-Verilog] EP3C40EDA_Exp31_SAD_DA_Test DL : 0: CycloneIII系列芯片EP3C40F780C8 SAD_DA 实验工程代码-CycloneIII，EP3C40F780C8，SAD_DA code
Date : 2025-12-21 Size : 2.05mb User :
[VHDL-FPGA-Verilog] fir_filter_50Mhz DL : 0: 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
Date : 2025-12-21 Size : 8.37mb User : Eason
[VHDL-FPGA-Verilog] cic_cq DL : 0: 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware description language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
Date : 2025-12-21 Size : 1.13mb User : 汪少锋
[VHDL-FPGA-Verilog] cic_cz DL : 0: 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware description language CIC interpolation filter, through the simulation in Modelsim software, including the complete project code, can be directly downloaded to the FPGA operation
Date : 2025-12-21 Size : 1.04mb User : 汪少锋
[VHDL-FPGA-Verilog] NCO_test DL : 0: FPGA的压控振荡器NCO完整Verilog工程代码，测试输出1KHZ sin波。signaltap抓取没问题。-VCO NCO complete FPGA Verilog code engineering, test output 1KHZ sin wave. signaltap crawl no problem.
Date : 2025-12-21 Size : 8.75mb User : allcot
[VHDL-FPGA-Verilog] VHDL-key-point-of-study-and-example DL : 0: 本人多年工程实践及学习总结得到的VHDL学习及应用关键知识点及工程代码示例-VHDL key point of study and good example
Date : 2025-12-21 Size : 1.03mb User : ranrer
[VHDL-FPGA-Verilog] 8bits DL : 0: 用Verilog语言模拟的8位优先编码器，可作为课堂作业实用，是完整工程代码-Using Verilog language simulation of the 8 priority encoder, can be used as a classroom operation, is a complete code
Date : 2025-12-21 Size : 100kb User : ww
[VHDL-FPGA-Verilog] Binary-BCD-code DL : 0: 用Verilog语言写的二进制转BCD码,可以作为课堂教学实验或者课后作业，有完整工程代码-Written in Verilog language transfer binary BCD code, can be used as a teaching experiment or the homework, a complete project code
Date : 2025-12-21 Size : 180kb User : ww
[VHDL-FPGA-Verilog] src DL : 0: v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
Date : 2025-12-21 Size : 8.67mb User : 南华真人

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