Search - vhdl delay

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[SCM] programe DL : 0: 项目程序，vhdl+C语言开关等时性测量，测量多子开关的延时时间-Project procedures, vhdl+ C language switch isochronism measured Multi-switch delay time
Date : 2026-01-10 Size : 495kb User : xbr
[SCM] ys DL : 0: 两路单极性HDB3+和HDB3-信号，经映射模块后完成单极性到双极性信号的数字转化，该模块由设计文件ys.v完成。由于映射后得到的是双极性归零码，通过该模块得到双极性非归零码。该模块由设计文件delay.v完成-Two unipolar HDB3-signals HDB3+, and by the mapping module to complete unipolar to bipolar signal digital conversion, the module completed by the design documents ys.v. As the map is obtained by bipolar zero code, through the module are bipolar NRZ. The module is completed by the design documents delay.v
Date : 2026-01-10 Size : 1kb User : 筱筱