Search - verilog 8 bit comparator

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[ARM-PowerPC-ColdFire-MIPS] vivado DL : 0: 用中规模MSI基本逻辑功能模块实现关模比较器（要求分别使用中规模和语言实现）：功能要求：它的输入是两个8位无符号二进制整数X和Y，以及一个控制信号S；输出信号为1个8位无符号二进制整数Z。输入输出关系为：当S=1时， Z=min(X,Y)；当S=0时， Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale and language are required respectively): Functional requirements: Its input is two 8-bit unsigned binary integers X and Y, and a control signal S; the output signal is an 8-bit unsigned binary integer Z. The relationship between input and output is: when S = 1, Z = min (X, Y); when S = 0, Z = max (X, Y).)
Date : 2025-12-27 Size : 10kb User : 瘾1581