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[ARM-PowerPC-ColdFire-MIPS] Pipeline模拟 DL : 1: 计算机体系结构中关于通用5级流水线的模拟实现程序-computer architecture on the common five Pipeline Simulation procedures
Date : 2025-12-21 Size : 412kb User : 欧未然
[ARM-PowerPC-ColdFire-MIPS] MIPS DL : 0: mips处理器指令仿真器，可查看流水线执行方式-mips instruction processor emulator, you can review the pipeline implementation
Date : 2025-12-21 Size : 968kb User : 魏继增
[ARM-PowerPC-ColdFire-MIPS] MIPS DL : 1: 带分支预测的MIPS流水线的verilog原代码。详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Date : 2025-12-21 Size : 17kb User : 张鹤
[ARM-PowerPC-ColdFire-MIPS] pipeline DL : 0: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Date : 2025-12-21 Size : 2.89mb User : kevin
[ARM-PowerPC-ColdFire-MIPS] volume-corrector DL : 0: 通过msp430F427的SD16模块测量气体的温度。压力信号最终对管道天然气进行体积修正-The SD16 module by msp430F427 measure gas temperature. Signal the end of the pipeline gas pressure to volume correction
Date : 2025-12-21 Size : 5kb User : 刘yi
[ARM-PowerPC-ColdFire-MIPS] STM-STM8 DL : 0: STM8 – introduction to family STM8S family of general-purpose 8-bit Flash microcontrollers offers ideal solutions for industrial and appliance market requirements. An advanced core version combined with a 3-stage pipeline ranks the STM8S microcontroller in the top position for performance versus cost. The true embedded EEPROM and the calibrated RC oscillator bring a significant cost effectiveness to the majority of applications.
Date : 2025-12-21 Size : 538kb User : PEN
[ARM-PowerPC-ColdFire-MIPS] CPU-tool-chain-design DL : 0: 摘要：EDA技术的成熟和进步，缩短了微处理器硬件设计和综合的周期。同时，开发工具链设计的自动化，已成了高效率、高质量嵌入式微处理器设计的重要内容。本文提出了采用体系结构描述语言(ADL)实现微处理器开发工具链自动设计的有效方法。针对ADL描述流水线的局限性，进行了扩展改进，因而使改进后的ADL能用来直接描述流水线。新方法在CK幸CORE开发工具链设计中的应用表明，比用GNU工具链功效有了显著提高。-Abstract: EDA technologies mature and progress, reducing microprocessor hardware design and integrated cycle. Meanwhile, the development tool chain design automation, has become a high efficiency, high quality an important part of the embedded microprocessor design. In this paper, architecture description language used (ADL) to achieve automatic design of microprocessor development tool chain and effective method. ADL describes the pipeline for the limitations is extended to improve, thereby improved ADL can be used to directly describe the pipeline. Fortunately, the new method in CK CORE development tool chain design that use the GNU tool chain effects than have been significantly improved.
Date : 2025-12-21 Size : 383kb User : 李立
[ARM-PowerPC-ColdFire-MIPS] cpu DL : 0: 16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
Date : 2025-12-21 Size : 5kb User : sean
[ARM-PowerPC-ColdFire-MIPS] RNTU DL : 0: 采用avr vusb代码，制作一个用于模拟飞行的无线电调谐组件的界面，采用160128点阵液晶，驱动芯片6963，并通过usb控制管道传送信息-To adopt code for avr vusb, to make a the radio tuning component interface for Flight Simulator, with 160,128 dot matrix LCD driver IC 6963 pipeline transmission of information and control via usb
Date : 2025-12-21 Size : 2.32mb User : 陈笑慰
[ARM-PowerPC-ColdFire-MIPS] PipelineCPU DL : 1: 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU differences that each of the five pipeline stages maintenance a variable (SelType) indicates that the currently executing instruction types, this treatment data Adventure loaduse adventure or jump adventure when each segment can know The statement is being processed, in order to facilitate our processing.
Date : 2025-12-21 Size : 10.83mb User : 武翔宇
[ARM-PowerPC-ColdFire-MIPS] MIPS789 DL : 1: 一个32位的5 级流水线处理器。在构架这个处理器的结构过程中是按照MIPS指令进行各个流水段的功能划分，并且在处理各种相关的时候参照了手头上的一个GCC_MIPS的C 语言编译器，因此支持MIPS 1指令系统。编译器的支持使这个核心有了实用价值，这个核心可以应用于各种嵌入式系统设计，代替常规的单片机实现片上系统，还可以在一个芯片里加入多个内核并且灵活的总线连接实现多处理器设计。-A 32-bit pipelined processor 5. In the framework of this processor architecture is based on the MIPS instruction process for each pipeline segment, function, and in dealing with a variety of related reference to have on hand when a GCC_MIPS C language compiler, and therefore supports MIPS 1 instruction. Compiler support to make this core has practical value, the core can be applied to a variety of embedded system design, instead of the conventional single-chip system on a chip, you can also add multiple cores in a single chip and flexible bus connection to multi-processing
Date : 2025-12-21 Size : 3.55mb User : 阿斯顿
[ARM-PowerPC-ColdFire-MIPS] PipelineCPU DL : 0: 1. understand how to improve CPU performance 2. master the working principle of pipelined MIPS microprocessor. 3. understand the concept of data adventure, control risk and the solution of pipeline conflict. 4. mastering the testing method of pipelined MIPS microprocessor(this file contains 3 packs,which is developed in Xilinx ISE contain the basic functions of a typical CPU 5 stages:IF,ID,EX,MEM,WB for education only)
Date : 2025-12-21 Size : 619kb User : D.FRANCIS
[ARM-PowerPC-ColdFire-MIPS] 定时器实现流水灯 DL : 0: 实现STM32基于定时器流水灯功能，通过定时器TIM1控制实现，三个流水灯交替闪烁(Realization of STM32 Based on Timer Pipeline Lamp Function)
Date : 2025-12-21 Size : 4.98mb User : 流云无极