Search - Virtual Memory Management

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[ARM-PowerPC-ColdFire-MIPS] mmuos DL : 1: 这是一个不到2000行的操作系统，巧妙地利用ARM9 CPU的内存管理单元(MMU)实现进程的切换。ARM9的4G虚拟地址可分成128个进程空间，每个32M。虽然它们的虚拟地址(VA)都是0-(32M-1)，但是对应的MVA(Modified vitual address,由虚拟地址VA和进程号PID组合而来)不一样，设置MVA对应的页表指向不同物理地址就可以很方便地让各进程运行空间相互隔开。代码很少，注释丰富，希望能对想理解操作系统、了解ARM体系结构的朋友有所帮助。 -This is a trip of less than 2000 operating system, cleverly using ARM9 CPU memory management unit (MMU) to achieve the switching process. ARM9 4G virtual address can be divided into 128 process space, each 32M. While their virtual address (VA) are 0- (32M-1), but the corresponding MVA (Modified Virtual address, and by the virtual address VA and the process of portfolio from PID) not the same, set MVA corresponding page table at the different physical address can be very easy to let the the process of separating the mutual operation of space. Code rarely Notes rich, in hopes of understanding the operating system, understanding the ARM architecture friends help.
Date : 2025-12-31 Size : 75kb User : 韦东
[ARM-PowerPC-ColdFire-MIPS] s3c2410_MMU DL : 0: 关于s3c2410 如何操作MMU（虚拟内存管理）的文档，有助于了解三星的ARM原理-S3C2410 how to operate on the MMU (virtual memory management) of documents, help to understand the principle of Samsung
Date : 2025-12-31 Size : 260kb User : 江涛涛
[ARM-PowerPC-ColdFire-MIPS] User_manual_2410x DL : 0: This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2410X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
Date : 2025-12-31 Size : 1.92mb User : Quang Truong