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[Embeded-SCM Develop] memoire_alphabet DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Date : 2008-10-13 Size : 1.21kb User : 秦拣俭
[Embeded-SCM Develop] VHDLRAM DL : 0: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Date : 2008-10-13 Size : 30.18kb User : 刘浏
[Embeded-SCM Develop] dualportRAM DL : 0: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Date : 2008-10-13 Size : 88kb User : 王雪松
[Embeded-SCM Develop] memoire_alphabet DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Date : 2026-01-03 Size : 1kb User : 秦拣俭
[Embeded-SCM Develop] VHDLRAM DL : 0: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Date : 2026-01-03 Size : 30kb User : 刘浏
[Embeded-SCM Develop] dualportRAM DL : 0: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation
Date : 2026-01-03 Size : 88kb User : 王雪松
[Embeded-SCM Develop] moore DL : 0: Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.-Moore-type state machine design, based on VHDL. Be able to read and write cycle of microprocessors, corresponding memory output enable WE write and read enable signal OE.
Date : 2026-01-03 Size : 25kb User : weixiaoyu
[Embeded-SCM Develop] r_w_flash DL : 1: FPGA高速完成AD采集回来的数据进行高速读写FLASH存储-AD Acquisition completion of FPGA high-speed data back to high-speed read and write FLASH memory
Date : 2026-01-03 Size : 880kb User : 王瓶
[Embeded-SCM Develop] AT24C08_Controller DL : 0: AT24C08 is a memory controller for SPI 8Mb memory
Date : 2026-01-03 Size : 44kb User : Vijay Baraiya
[Embeded-SCM Develop] Flash_FPAG_JTAG DL : 0: FPGA或者CPLD通过JTAG接口对FLASH进行读写的资料。非常有用-Programming Flash Memory from FPAGs and CPLDs Using the JTAG Port. Very useful
Date : 2026-01-03 Size : 298kb User : superstar
[Embeded-SCM Develop] NAND_FLASH_simulation_model DL : 0: Date : 2026-01-03 Size : 830kb User : andrew zhang
[Embeded-SCM Develop] DIANZIQIN DL : 0: 实现琴键记忆及动态显示的电子琴VHDL源程序，经FPGA验证可行-Achieve the keys of the keyboard memory and dynamic display VHDL source code, after FPGA validation feasible
Date : 2026-01-03 Size : 2kb User : 王宇坤
[Embeded-SCM Develop] VHDLmipsPipeline DL : 0: 32 位MIP流水线CPU设计，5 stage，代码详细，包括ALU,存储器,寄存器等，是个很不错的CPU设计-32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
Date : 2026-01-03 Size : 548kb User : suborong
[Embeded-SCM Develop] ElectronicLocks DL : 0: 电子密码锁为三位密码，由输入部分，控制部分和输出部分组成。其中输入部分包括4×4矩阵键盘、弹跳消除电路、键盘扫描电路、键盘译码电路；控制部分包括按键存储电路、密码修改电路、比较电路；输出部分主要是七段译码显示器。当输入三位正确密码时，一个L1发光二极管亮，指示门打开；当输入密码错误时，另外一个发光二极管亮，此时可以通过开锁开关（复位开关）重新输入密码。若想实现密码更改，可重新按下上锁开关设置密码，即实现密码更改功能。-Electronic locks on the three passwords, the input, the control section and output components. Enter some of which include 4 × 4 matrix keyboard, bounce elimination circuit, the keyboard scanning circuit, the keyboard decoder circuit control section includes key memory circuits, the password modify the circuit to compare the circuit output part of the main seven-segment display decoder. When you enter the correct password three, a L1 LED light to indicate the door open When you enter your password wrong, the other a light-emitting diode light, then you can unlock switch (reset switch) to re-enter the password. To achieve the password changes, press the lock switch can be re-set the password, that password change functionality to achieve.
Date : 2026-01-03 Size : 41kb User : sunnan
[Embeded-SCM Develop] Micro-program DL : 0: 微程序控制电路是CPU 控制器的核心电路，控制产生指令执行时各部件协调工作所需的所有控制信号，以及下一条指令的地址。微程序控制器的组成如图6-12 所示，主要由三个部分组成，分别是微指令控制电路、微地址寄存器和微指令存储器lpm_rom 其中微指令控制电路用组合电路对指令中的1[7..2] 、操作台控制信号SWA 和SWB 的状态、状态寄存器的输出状态FC 、FZ ，产生微地址变化的控制信号，实现对微地址控制:微地址寄存器控制电路的基本输入信号是微指令存储器的下地址字段M[6..1] ，同时还受微指令控制电路的输出信号SE[6..1]和复位信号RST 的控制，输出下一个微指令的地址:控制存储器由FPGA 中的LPM ROM 构成，输出24 位控制信号。在24 位控制信号中，微命令信号为18 位，微地址信号豆位。在口时刻将打入微地址寄存器UA 的内容，即为下一条微指令地址.当T4时刻进行测试判别时，转移逻辑满足条件后输出的负脉冲，通过强制端将某一触发器置为"1"状态，完成地址修改。微程序控制器中的微控制代码可以通过对FPGA 中LPMß OM 的配置进行输入，通过编辑LPM ROM.mif 文件来修改微控制代码。详细情况可参考LPIÞ CROM的配置方法。微指令控制电路内部结构如图6-2 ， 6-3. 6-13 所示-Micro-program control circuit is the core CPU controller circuit, the control instruction execution produces the coordination of all parts of all the necessary control signals, and the next instruction address. The composition of micro-program controller shown in Figure 6-12, the main three components, namely, microinstruction control circuit, micro-address register and the microcode memory lpm_rom microcode control circuit which combination circuit with instruction in the 1 [ 7 .. 2], SWA and SWB console control signal state, the state register output state FC, FZ, produce changes in micro-address control signals, to realize the micro-address control: micro-address register control circuit input signal is the basic micro- The next address field instruction memory M [6 .. 1], but also by the microcode control circuit output signal SE [6 .. 1] and reset control signal RST, the output of the next microinstruction address: control memory by the FPGA in the LPM ROM form, the output 24-bit
Date : 2026-01-03 Size : 2.46mb User : 623902748
[Embeded-SCM Develop] memoire_alphabet DL : 0: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Date : 2026-01-03 Size : 1kb User : romMay