Search - fpga ram

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[Embeded-SCM Develop] fpga_ram_flash DL : 0: 一个fpga开发板的原理图，此板具有led灯、ram、flash-an fpga development board diagram, the board has led lights, ram, flash
Date : 2008-10-13 Size : 107.94kb User : xuyang
[Embeded-SCM Develop] fpga_ram_flash DL : 0: 一个fpga开发板的原理图，此板具有led灯、ram、flash-an fpga development board diagram, the board has led lights, ram, flash
Date : 2025-12-22 Size : 108kb User : xuyang
[Embeded-SCM Develop] cpld_fpga_sample_program DL : 0: 全是FPGA的例子对大家应该有好处大家赶快下把知识不等人-are examples we should be beneficial to everyone as soon as possible under the knowledge from people
Date : 2025-12-22 Size : 240kb User : sss
[Embeded-SCM Develop] xilinx DL : 0: xilinx 开发板原理图,里面含有pcb图,自己完全可以做一块来玩,不用买别人的,很省钱,又锻炼了自己.-Xilinx development board schematic diagram, which contains pcb chart their own can make a play, do not buy someone else
Date : 2025-12-22 Size : 298kb User : 萧勇
[Embeded-SCM Develop] fifov1 DL : 0: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、与写时钟同步的写有效（wren）和写数据（wr_data）、与读时钟同步的读有效（rden）和读数据（rd_data）为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Date : 2025-12-22 Size : 370kb User : lsg
[Embeded-SCM Develop] TESTRAM DL : 0: FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much about the use of! Simulation software platform QUARTUSII8.0 through!
Date : 2025-12-22 Size : 437kb User : wangzhaohui
[Embeded-SCM Develop] ramtest DL : 0: 用verilog语言往内部FPGA的sram中读写数据，即把1—4写入ram的1—4的地址里-Verilog language within the FPGA with the sram to read and write data, that is 1-4, 1-4 to write the address in ram
Date : 2025-12-22 Size : 57kb User : 蓝冰
[Embeded-SCM Develop] The_dual-port_RAM-based_FPGA DL : 0: 基于FPGA的双口RAM实现及应用,对RAM有一个系统的介绍-The dual-port RAM-based FPGA Implementation and Application of RAM to have a systematic introduction
Date : 2025-12-22 Size : 330kb User : 马亚宁
[Embeded-SCM Develop] emifa_ram DL : 0: 基于EMIF 的ram空间程序设计，适合fpga和新手(EMIF based RAM space programming, suitable for FPGA and novices)
Date : 2025-12-22 Size : 1kb User : CrazyICer