Search - VHDL fifo

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[Embeded-SCM Develop] 通用存储器包括各种类型存储器的VHDL描述 DL : 0: 通用存储器包括各种类型存储器的VHDL描述，如FIFO，双口RAM等VHDL代码库
Date : 2009-03-03 Size : 603.34kb User : hanker3
[Embeded-SCM Develop] fifov1 DL : 0: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、与写时钟同步的写有效（wren）和写数据（wr_data）、与读时钟同步的读有效（rden）和读数据（rd_data）为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Date : 2026-01-02 Size : 370kb User : lsg
[Embeded-SCM Develop] VHDL DL : 0: 常见的输入输出及存储器件（ram及fifo）vhdl实现-The vhdl source codes of ram,fifo.
Date : 2026-01-02 Size : 22kb User : xugx
[Embeded-SCM Develop] fifo_core DL : 0: 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
Date : 2026-01-02 Size : 10kb User : 刘太联
[Embeded-SCM Develop] afifo_0916 DL : 0: 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
Date : 2026-01-02 Size : 151kb User : 范小虎
[Embeded-SCM Develop] fifo DL : 0: FIFO的VHDL代码，最简单的同步FIFO设计，仅供参考-FIFO VHDL code
Date : 2026-01-02 Size : 394kb User : justin
[Embeded-SCM Develop] asyn_FIFO- DL : 0: A asynchronous FIFO is implemented. VHDL fil+ vsim.do script
Date : 2026-01-02 Size : 25kb User : 许日升
[Embeded-SCM Develop] TransfData DL : 0: 用于FPGA发送数据，采用VHDL语言编程，采用16位fifo发送，内涵时钟、复位、使能信号-FPGA is used to send data, using VHDL language programming, using 16 fifo sent connotation clock, reset, enable signal
Date : 2026-01-02 Size : 1kb User : 王强