Search - VHDL fifo

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[Com Port] async_fifo DL : 0: 异步fifo 源程序代码欢迎大家学习用VHDL语言编写-asy fifo
Date : 2026-01-02 Size : 208kb User : chenxuhui
[Com Port] uart16550 DL : 0: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Date : 2026-01-02 Size : 1.68mb User : CloudZhang
[Com Port] UART16550 DL : 0: UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
Date : 2026-01-02 Size : 8kb User : huangluyang