Search - memory vhdl

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[Other] sdram32 DL : 0: sram 存储器控制程序很完整，值得认真研究，很有帮组-SRAM memory control program is very complete, worthy of serious study, is to help groups
Date : 2026-01-03 Size : 23kb User : 许曲
[Other] FIFO_Memory DL : 0: VHDL设计——FIFO存储器设计-VHDL design-- FIFO design
Date : 2026-01-03 Size : 7kb User : 钱伟康
[Other] DDR_allegro DL : 0: 用allegro画的ddr存储器电路。六层板设计，很好的参考资料-Allegro painting with ddr memory circuit. Six-storey plate design, very good reference
Date : 2026-01-03 Size : 364kb User : 朱宝军
[Other] uc_interface DL : 0: This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system. -This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system.
Date : 2026-01-03 Size : 4kb User : alex
[Other] sram DL : 0: to write and read from an sram. its actually a logic cell,when the write enable is high its possible to write data onto a memory location when read enable is high we can read the data in given memory location
Date : 2026-01-03 Size : 37kb User : mariamma
[Other] Memory DL : 0: 计算机组成原理简单的存储器程序，仅供大家参考。-Principles of Computer Organization simple memory procedures, only reference.
Date : 2026-01-03 Size : 228kb User : 于洪宇
[Other] 91_WSS DL : 0: 实现窗口搜索算法的并行系统——序列存储器-Search algorithm to achieve the window parallel systems- Serial Memory
Date : 2026-01-03 Size : 2kb User : yeyang
[Other] 92_WSS DL : 0: 实现窗口搜索算法的并行系统——字符串存储器-Search algorithm to achieve the window parallel systems- the string memory
Date : 2026-01-03 Size : 3kb User : yeyang
[Other] P6_Cache DL : 0: MEMORY CACHE SIMPLE CODE
Date : 2026-01-03 Size : 12.25mb User : anaterremoto
[Other] Bufor DL : 0: Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
Date : 2026-01-03 Size : 503kb User : Kozinio
[Other] FIFO DL : 0: fifo的实现，可以作用于memory的数据传输等地方，在fpga上实现，可以进行综合和仿真-fifo implementation, you can act on memory data transfer and other places, in the fpga to achieve, to undertake a comprehensive and Simulation
Date : 2026-01-03 Size : 6kb User : zz
[Other] dds DL : 0: 块DDS芯片中主要包括频率控制寄存器、高速相位累加器和正弦计算器三个部分（如Q2220）。频率控制寄存器可以串行或并行的方式装载并寄存用户输入的频率控制码；而相位累加器根据dds频率控制码在每个时钟周期内进行相位累加，得到一个相位值；正弦计算器则对该相位值计算数字化正弦波幅度（芯片一般通过查表得到）。DDS芯片输出的一般是数字化的正弦波，因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。 -In the programming step, the electronic controller fills the memory with data. Each datum is a binary word representing the amplitude of the signal at an instant of time. The array of data in the memory then forms a table of amplitudes, with time implied by the position in the table. If, for example, the first half of the table were filled with zeroes and the second half with values of 100 , then the data would represent a square wave. Any other wave shape can be created simply by altering the data. Devices are also available that cannot be programmed, and can only output sinewaves or a small number of waveforms.
Date : 2026-01-03 Size : 5kb User : 李彦伟
[Other] MX29LV128D DL : 0: 128M-BIT CMOS Voltage 3V Flash Memory
Date : 2026-01-03 Size : 13kb User : rillyxue
[Other] dualportram_vhdl DL : 0: 采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化-VHDL hardware description language using the dual-caliber RAM block memory initialization
Date : 2026-01-03 Size : 2kb User : sharbel
[Other] Access-memory DL : 0: 用vhdl写的一个存储器访问程序，下载到FPGA运行通过，有助于了解memory的工作原理。-The vhdl write a memory access program, downloaded to the FPGA to run through the help understand memory works.
Date : 2026-01-03 Size : 210kb User : lei liming
[Other] onfi_phy_if DL : 0: 大容量存储器，Nandflash控制的VHDL实现代码，经验证时序正常，器件可以正常工作。-Large-capacity memory, Nandflash control VHDL implementation code, proven normal sequence, the device is working properly.
Date : 2026-01-03 Size : 7kb User : 画生
[Other] 2 DL : 0: 用VHDL语言设计一个8位双向可控移位寄存器。移位寄存器由D型触发器构成，采用串入并出形式。采用VHDL方式设计一个16х4位RAM存储器-VHDL language to design an 8-bit bidirectional shift register controllable. The shift register by a D-type flip-flops, using the string into and out of form. Way design using VHDL a bit RAM memory 16х4
Date : 2026-01-03 Size : 1kb User : 赵丽丽
[Other] ram DL : 0: This file is about create memory in ISE by VHDL language.
Date : 2026-01-03 Size : 11kb User : najme.yousefi