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[Other] wave0001 DL : 0: 在MAX-PLUS下设计的函数消耗发生器，波形有正弦波、方波、三角拨、锯齿波（用键盘选择），信号频率可调（用键盘调节）-the MAX-PLUS design of the consumption function generator, a sine wave, square, triangle area and Sawtooth (keyboard), in signal frequency adjustable (keyboard conditioning)
Date : 2025-12-23 Size : 130kb User : 曹海学
[Other] VHDL-FPGA-clock DL : 1: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Date : 2025-12-23 Size : 263kb User : 王越
[Other] MaxPlusII DL : 0: Designing with MAX+PLUS -Designing with MAX+ PLUS
Date : 2025-12-23 Size : 884kb User : 陈宏
[Other] f_add DL : 0: 本文件包是在MAX+plus II 软件环境下实现半加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve a half-adder logic function
Date : 2025-12-23 Size : 12kb User : 罗理平
[Other] h_adder DL : 0: 本文件包是在MAX+plus II 软件环境下实现全加器的逻辑功能-This document packet was MAX+ Plus II software environment to achieve full adder logic function
Date : 2025-12-23 Size : 13kb User : 罗理平
[Other] mendianlu DL : 0: 本文件包是在MAX+plus II 软件环境下验证门电路的逻辑功能-This document packet was MAX+ Plus II software environment to verify the logic function circuit door
Date : 2025-12-23 Size : 12kb User : 罗理平
[Other] count DL : 0: 本文件包是在MAX+plus II 软件环境下实现计数器的逻辑功能-This document packet was MAX+ Plus II software environment counters realize the logic function
Date : 2025-12-23 Size : 57kb User : 罗理平
[Other] 1_061227123744 DL : 0: max plus的入门与应用，适合初学者对max plus ii有一个感性的认识-max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of
Date : 2025-12-23 Size : 232kb User : da
[Other] clock DL : 0: 本文介绍一种利用 EDA技术和VHDL 语言 ,在MAX+PLUSⅡ环境下,设计了一种新型的智能密码锁。它体积小、功耗低、价格便宜、安全可靠,维护和升级都十分方便,具有较好的应用前景-This paper presents a use of EDA technologies and VHDL language, in MAX+ PLUS Ⅱ environment, design a new type of intelligent locks. Its small size, low power consumption, cheap, safe, reliable, maintenance and upgrade are very convenient, has good application prospects
Date : 2025-12-23 Size : 66kb User : 叶仔
[Other] CPLDMAXplus DL : 0: CPLD数字电路设计——使用MAX+plusⅡ入门篇.rar 不能错过的书籍-CPLD digital circuit design- the use of MAX+ Plus Ⅱ entry papers. Rar can not miss books
Date : 2025-12-23 Size : 12.72mb User : twinslizzy
[Other] EDA DL : 0: 基于MAX PLUS 2 FPGA 依据状态机结构的10禁止计数器内附其仿真图-MAX PLUS 2 FPGA based state machine based on the structure of the 10 counter containing the prohibition of the simulation map
Date : 2025-12-23 Size : 11kb User : yuqingwei
[Other] traffic DL : 0: 实现路口交通灯系统的控制方法很多，可以用标准逻辑器件，可编程控制器PLC，单片机等方案来实现。但是这些控制方法的功能修改及调试都需要硬件电路的支持，在一定程度上增加了功能修改及系统调试的困难。因此，在设计中采用EDA技术，应用目前广泛应用的Verilog HDL硬件电路描述语言，实现交通灯系统控制器的设计，利用MAX+PLUS 集成开发环境进行综合、仿真，并下载到CPLD可编程逻辑器件中，完成系统的控制作用。-Intersection traffic signal systems to achieve the control of many ways you can use standard logic devices, programmable logic controller PLC, microcontroller and other programs to achieve. However, the functions of these control methods require modification and debugging support for hardware circuit, to a certain extent, an increase of functional modifications and system debugging difficulties. Thus, in the design using EDA technologies, applications, the widely used Verilog HDL hardware circuit description language to realize the design of traffic signal system controller, using MAX+ PLUS a comprehensive integrated development environment, simulation, and downloaded to the CPLD programmable logic devices to complete the system control role.
Date : 2025-12-23 Size : 1kb User : 沈田
[Other] MaxPlusChineseTuturial DL : 0: max-plus 简单用户使用入门指南。包括软件安装，图形设计，编译，定时分析，器件编程等详细介绍。-Max+Plus II Chinese Tuturial
Date : 2025-12-23 Size : 404kb User : 文静
[Other] sy1_yt DL : 0: 在max-plus 环境下使用vhdl语言实现用半加器组成全加器的功能。-In the max-plus environment, using vhdl language component with half adder full adder function.
Date : 2025-12-23 Size : 80kb User : cy
[Other] 100vhdlsimple DL : 0: 100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的-100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation
Date : 2025-12-23 Size : 228kb User : 刘超
[Other] Maxplus2_Tut_v3.0 DL : 0: max plus book. tutariol.
Date : 2025-12-23 Size : 77kb User : sce
[Other] MaxPPlus-II DL : 0: maxplusII教程 Max+Plus II 简易用户使用入门指南-maxplusII teaching material Simple user use portal guide
Date : 2025-12-23 Size : 228kb User : sherry
[Other] verilog_hdl DL : 0: You can now read the brochure in the Quartus II. Altera ® the Quartus ® II design software is suitable for The most comprehensive single-chip programmable system (SOPC) design environment. If you have previously used MAX + PLUS ® II software, and other design software or ASIC design software and are ready to switch Quartus II software, or if you have some understanding of the Quartus II software, but want to learn more Its functions, this manual is for you. -verilog_hdl Language Tutorial
Date : 2025-12-23 Size : 1.28mb User : 任耀庭
[Other] accumulator DL : 0: accumulator max plus
Date : 2025-12-23 Size : 5kb User : rls1324
[Other] address_register DL : 0: address register max plus
Date : 2025-12-23 Size : 3kb User : rls1324

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