Search - fpga ram

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[Other] my_ram_vhdl DL : 0: how to infer ram for fpga altera xilinx
Date : 2025-12-22 Size : 1kb User : yusuf.abdullah
[Other] FPGA-TWO-RAM DL : 0: 这样就可以在FPGA内实现双口RAM了-This can be achieved in the FPGA dual-port RAM
Date : 2025-12-22 Size : 4kb User : zhan
[Other] jj DL : 0: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
Date : 2025-12-22 Size : 534kb User : 黄奇家
[Other] read_wirte_ram DL : 0: FPGA实现双口RAM功能，从而用FPGA实现双控制器间的数据交换-FPGA realization of dual-port RAM functions, the exchange of data between the dual-controller with FPGA
Date : 2025-12-22 Size : 1kb User :
[Other] 635022219123437500 DL : 0: 基于FPGA的CAM设计，CAM设计的方案和代码。-Using Block RAM for High Performance Read/Write CAMs
Date : 2025-12-22 Size : 1.89mb User : 刘宁
[Other] FPGA-RAM-read-and-write-procedures DL : 0: FPGA读写RAM的程序，用FPGA实现RAM，并从单片机读写数据。-FPGA RAM read and write procedures
Date : 2025-12-22 Size : 399kb User : 李恩旭
[Other] ram_test DL : 0: ISE中双端口不同位宽ram的数据存储，包括testbench-veirlog ram FPGA
Date : 2025-12-22 Size : 2.52mb User : 安娜
[Other] RAM DL : 0: 通过使用fpga，verilog语言来实现RAM的读写功能。-for ram reading and writing
Date : 2025-12-22 Size : 4.39mb User : 言艳
[Other] 75_RAM DL : 0: fpga中对RAM的VHDL程序，非常之实用(FPGA in the RAM VHDL procedures, very practical)
Date : 2025-12-22 Size : 1kb User : 猪头2005
[Other] Block_RAM DL : 0: ditributed ram in fpga and block ram in fpga
Date : 2025-12-22 Size : 1.12mb User : ghanbari1995