Search - divider verilog code

Search - divider verilog code - List

[Other] Verilog1 DL : 0: 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
Date : 2025-12-19 Size : 2kb User : yangningcong
[Other] verilog_fenpin0 DL : 0: 这是一个verilog分频代码，代码比较简洁.-This is a divider verilog code, the code is relatively simple.
Date : 2025-12-19 Size : 3kb User : min_ming
[Other] ex1_clkdiv DL : 0: Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
Date : 2025-12-19 Size : 392kb User : 王海波
[Other] streamline_div DL : 0: 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
Date : 2025-12-19 Size : 1kb User : Andy Zhou