Search - different frequency in vhdl

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[Communication] 3FSK.vhd DL : 0: 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation method to achieve 3FSK. The input of the system clock frequency respectively 2 hours, 4 minutes and 8 frequency-divider to have these three kinds of frequencies. Through the digital baseband signals received three pairs of binary-coded level value, and use them as three elected a switch to a different frequency values were selected, select a different signal, in order to achieve 3FSK modulation.
Date : 2025-12-22 Size : 4kb User : 雷月