Search - segment vhdl

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[Windows Develop] clock_control DL : 0: 用vhdl语言描述时钟的功能，并通过七段译码输出。-VHDL language used to describe the function of the clock and through the Seven-Segment decoder output.
Date : 2026-01-09 Size : 65kb User : wuyub
[Windows Develop] fVerrilog_Devr DL : 0: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL source code quite popular, she will Verilog source together with contribution to everyone: eight priority encoder, multipliers, multiplexers binary switch the BBCD code, adder, subtracter, simple straightforward state machine, four comparators, 7-segment LED, i2c bus, lcd LCD LCD display, DIP switch, serial port, buzzer, matrix keyboard, Marquee, traffic lights, digital clock can be used directly.
Date : 2026-01-09 Size : 3.02mb User : qtzx
[Windows Develop] xuehao2 DL : 0: VHDL语言实现10位学号在七段数码管上的显示，并且学号由左右两侧分别一一向中间逐个显示，能够实现多组不同的学号实现-VHDL language to achieve 10 number in the seven segment digital tube display, and the number of left and right sides respectively by one one to the middle one display, can realize the different groups of its implementation.
Date : 2026-01-09 Size : 767kb User : 杨佳文