I have written a number of Verilog code, for beginners to learn, think it appropriate.

verilog_examples
................\compiler_directives
................\...................\ifdef.v
................\finite_state_machines
................\.....................\fsm_example.v
................\.....................\fsm_example2.v
................\.....................\fsm_example2_TB.v
................\.....................\fsm_example_TB.v
................\.....................\microcoded.v
................\.....................\microcoded_TB.v
................\functions
................\.........\fncdemo.v
................\.........\fncdemo_TB.v
................\mips
................\....\registers.txt
................\sequential
................\..........\freqdiv.do
................\..........\freqdiv.v
................\..........\freqdiv_tb.v
................\..........\seq4.v
................\..........\seq4_tb.v
................\system_tasks
................\............\data.txt
................\............\readmemh.v
................\testbenches
................\...........\combi_ckt.v
................\...........\combi_ckt_TB.v
................\...........\comments.v
................\...........\demo.v
................\...........\demo_TB.v
................\...........\taskdemo.v

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