Write their own tests using Verilog Xilinx development board vertex2 lighting one bright interval 2 seconds

test
....\test.bgn
....\test.bit
....\test.bld
....\test.cmd_log
....\test.drc
....\test.ipf
....\test.ise
....\test.ise_ISE_Backup
....\test.lfp
....\test.lso
....\test.ncd
....\test.ngc
....\test.ngd
....\test.ngr
....\test.ntrc_log
....\test.pad
....\test.par
....\test.pcf
....\test.prj
....\test.restore
....\test.stx
....\test.syr
....\test.twr
....\test.twx
....\test.ucf
....\test.unroutes
....\test.ut
....\test.v
....\test.xpi
....\test.xst
....\test_guide.ncd
....\test_map.map
....\test_map.mrp
....\test_map.ncd
....\test_map.ngm
....\test_pad.csv
....\test_pad.txt
....\test_prev_built.ngd
....\test_summary.html
....\test_summary.xml
....\test_usage.xml
....\xst
....\...\dump.xst
....\...\........\test.prj
....\...\........\........\ngx
....\...\........\........\...\notopt
....\...\........\........\...\opt
....\...\........\........\ntrc.scr
....\...\projnav.tmp
....\...\work
....\...\....\hdllib.ref
....\...\....\vlg34
....\...\....\.....\test.bin
....\_impact.cmd
....\_ngo
....\....\netlist.lst
....\_pace.ucf
....\_xmsgs
....\......\bitgen.xmsgs
....\......\map.xmsgs
....\......\ngdbuild.xmsgs
....\......\par.xmsgs
....\......\trce.xmsgs
....\......\xst.xmsgs

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