3DES encryption algorithm, introduced the principle and detailed description of the FPGA algorithm design. Use of state machine and pipelining technology, makes the size and speed to achieve the best optimization added input and output interface design to enhance the flexibility of the application of the algorithm. Each module are used hardware description language to achieve, and ultimately downloaded to the FPGA chip in Stratix EP1S25F780C5.

基于状态机和流水线技术的3DES加密算法及其FPGA设计.doc

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