Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)

divider
.......\divider.v
.......\div_ctl.v
.......\div_datapath.v
.......\div_tb.v
.......\read me.txt

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