This is a MIPS architecture to develop the CPU soft-core OR2000, higher than OR1200 version, there is also SOC procedures, many times MPW silicon success

r2000
.....\conmax
.....\......\timescale.v
.....\......\wb_conmax_arb.v
.....\......\wb_conmax_defines.v
.....\......\wb_conmax_master_if.v
.....\......\wb_conmax_msel.v
.....\......\wb_conmax_pri_dec.v
.....\......\wb_conmax_pri_enc.v
.....\......\wb_conmax_rf.v
.....\......\wb_conmax_slave_if.v
.....\......\wb_conmax_top.v
.....\mem
.....\...\asram_core.v
.....\or2000pl
.....\........\define.h
.....\........\r2000_alu.v
.....\........\r2000_aluctrl.v
.....\........\r2000_bradecoder.v
.....\........\r2000_comparator.v
.....\........\r2000_cp0.v
.....\........\r2000_cpu.v
.....\........\r2000_cpu_pipe.v
.....\........\r2000_d-cache.v
.....\........\r2000_decoder.v
.....\........\r2000_divisor.v
.....\........\r2000_forward.v
.....\........\r2000_i-cache.v
.....\........\r2000_membus.v
.....\........\r2000_multdiv.v
.....\........\r2000_multiplier.v
.....\........\r2000_mux2.v
.....\........\r2000_mux3.v
.....\........\r2000_mux4.v
.....\........\r2000_mux5.v
.....\........\r2000_mux7.v
.....\........\r2000_pc.v
.....\........\r2000_pipe.v
.....\........\r2000_pipe_ctrl.v
.....\........\r2000_regfile.v
.....\........\r2000_regfile.v.bak
.....\........\r2000_shifter.v
.....\........\timescale.v
.....\r2000_soc
.....\.........\r2000_soc.v
.....\testbench
.....\.........\idt71v416s10.v
.....\.........\SRAM.v
.....\.........\tb_r2000_soc.v

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