MSP430 the nRF905 place for high level, "TRX_CE" pin "TX_CE pins for low level after etching association data, the design of CPU in 35 seconds have been set by judge Nrf9051" DR "whether the pin is getting taller, if high is proved valid data is received, you can exit the receive mode, weak consistent not accept 2 to stay time also exit is received by the module, then exit in standby module, CPU inside the nRF905 receive data through the SPI bus register data readout, namely receive moral effective data. Portable to accept part of the program, there is a little it should be noted that a lot of data are not mentioned, is after sending the command byte read CPU on MOSI line "MISO" signal on nRF905 will automatically return a byte of data, the status register of the information itself, the subsequent receiving data does not automatically follow the output, only the CPU on MOSI output a byte (can be a random value), nRF905 will only be on the "MISO" returns a byte, CPU, nRF905 will be full again, until it is finished.

MSP430_nRF905.txt

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