Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.

WorkOneBetaC
............\Accumulater.v
............\Accumulater.v.bak
............\Adapter.v
............\Adjust.bsf
............\Adjust.v
............\Adjust.v.bak
............\db
............\..\altsyncram_4331.tdf
............\..\altsyncram_fp21.tdf
............\..\altsyncram_v531.tdf
............\..\prev_cmp_WorkOneBeta.asm.qmsg
............\..\prev_cmp_WorkOneBeta.eda.qmsg
............\..\prev_cmp_WorkOneBeta.fit.qmsg
............\..\prev_cmp_WorkOneBeta.map.qmsg
............\..\prev_cmp_WorkOneBeta.sim.qmsg
............\..\prev_cmp_WorkOneBeta.tan.qmsg
............\..\wed.wsf
............\..\WorkOneBeta.asm.qmsg
............\..\WorkOneBeta.cbx.xml
............\..\WorkOneBeta.cmp.bpm
............\..\WorkOneBeta.cmp.cdb
............\..\WorkOneBeta.cmp.ecobp
............\..\WorkOneBeta.cmp.hdb
............\..\WorkOneBeta.cmp.logdb
............\..\WorkOneBeta.cmp.rdb
............\..\WorkOneBeta.cmp.tdb
............\..\WorkOneBeta.cmp0.ddb
............\..\WorkOneBeta.cmp_bb.cdb
............\..\WorkOneBeta.cmp_bb.hdb
............\..\WorkOneBeta.cmp_bb.logdb
............\..\WorkOneBeta.cmp_bb.rcf
............\..\WorkOneBeta.dbp
............\..\WorkOneBeta.db_info
............\..\WorkOneBeta.eco.cdb
............\..\WorkOneBeta.eda.qmsg
............\..\WorkOneBeta.fit.qmsg
............\..\WorkOneBeta.hier_info
............\..\WorkOneBeta.hif
............\..\WorkOneBeta.map.bpm
............\..\WorkOneBeta.map.cdb
............\..\WorkOneBeta.map.ecobp
............\..\WorkOneBeta.map.hdb
............\..\WorkOneBeta.map.logdb
............\..\WorkOneBeta.map.qmsg
............\..\WorkOneBeta.map_bb.cdb
............\..\WorkOneBeta.map_bb.hdb
............\..\WorkOneBeta.map_bb.logdb
............\..\WorkOneBeta.pre_map.cdb
............\..\WorkOneBeta.pre_map.hdb
............\..\WorkOneBeta.psp
............\..\WorkOneBeta.pss
............\..\WorkOneBeta.rpp.qmsg
............\..\WorkOneBeta.rtlv.hdb
............\..\WorkOneBeta.rtlv_sg.cdb
............\..\WorkOneBeta.rtlv_sg_swap.cdb
............\..\WorkOneBeta.sgate.rvd
............\..\WorkOneBeta.sgate_sm.rvd
............\..\WorkOneBeta.sgdiff.cdb
............\..\WorkOneBeta.sgdiff.hdb
............\..\WorkOneBeta.signalprobe.cdb
............\..\WorkOneBeta.sim.hdb
............\..\WorkOneBeta.sim.qmsg
............\..\WorkOneBeta.sim.rdb
............\..\WorkOneBeta.sim_ori.vwf
............\..\WorkOneBeta.sld_design_entry.sci
............\..\WorkOneBeta.sld_design_entry_dsc.sci
............\..\WorkOneBeta.syn_hier_info
............\..\WorkOneBeta.tan.qmsg
............\DDS.v
............\Degree.mif
............\FreFindTable.v
............\FreFindTable_bb.v
............\Hz.mif
............\Measure.bsf
............\Measure.v
............\Measure.v.bak
............\PhaseFindTable.v
............\PhaseFindTable_bb.v
............\PLL.bsf
............\PLL.ppf
............\PLL.v
............\PLL_bb.v

............\PLL_waveforms.html
............\prev_cmp_WorkOneBeta.qmsg
............\Read.bsf
............\Read.v
............\Read.v.bak
............\simulation
............\..........\activehdl
............\..........\.........\WorkOneBeta.vo
............\..........\.........\WorkOneBeta_v.sdo
............\SinFindTable.v
............\SinFindTable_bb.v
............\Sin_12b.mif
............\Strobe.bsf
............\Strobe.v
............\Strobe.v.bak
............\timing

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