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Title: 基于VHDL的DDS信号发生器 Download
  • Category:
  • 编译
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  • File Size:
  • 363byte
  • Update:
  • 2011-05-04
  • Downloads:
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  • Uploaded by:
  • meimeisa1
 Description: 本设计是利用EDA技术设计的电路, 该信号发生器输出信号的频率范围为20Hz～20KHz，幅度的峰 峰值为0.3V～5V两路信号之间可实现0°～359°的相位差。侧重叙述了用FPGA来完成直接数字频率合成器(DDS)的设计
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