It introduced a simple digital clock, verilog language. Including two digital clocks and digital two minutes and two seconds digits.

shuzizhong\asas.vwf
..........\Block2.bdf
..........\cmp_state.ini
..........\db\add_sub_3sh.tdf
..........\..\add_sub_mf8.tdf
..........\..\add_sub_nf8.tdf
..........\..\add_sub_ob8.tdf
..........\..\add_sub_of8.tdf
..........\..\add_sub_pf8.tdf
..........\..\add_sub_qf8.tdf
..........\..\alt_u_div_fmd.tdf
..........\..\lpm_divide_kmf.tdf
..........\..\lpm_divide_nef.tdf
..........\..\shuzizhong.cbx.xml
..........\..\shuzizhong.cmp.rdb
..........\..\shuzizhong.db_info
..........\..\shuzizhong.eco.cdb
..........\..\shuzizhong.eds_overflow
..........\..\shuzizhong.fnsim.cdb
..........\..\shuzizhong.fnsim.hdb
..........\..\shuzizhong.hier_info
..........\..\shuzizhong.hif
..........\..\shuzizhong.map.cdb
..........\..\shuzizhong.map.hdb
..........\..\shuzizhong.map.logdb
..........\..\shuzizhong.map.qmsg
..........\..\shuzizhong.pre_map.cdb
..........\..\shuzizhong.pre_map.hdb
..........\..\shuzizhong.psp
..........\..\shuzizhong.rpp.qmsg
..........\..\shuzizhong.rtlv.hdb
..........\..\shuzizhong.rtlv_sg.cdb
..........\..\shuzizhong.rtlv_sg_swap.cdb
..........\..\shuzizhong.sgate.rvd
..........\..\shuzizhong.sgdiff.cdb
..........\..\shuzizhong.sgdiff.hdb
..........\..\shuzizhong.sim.hdb
..........\..\shuzizhong.sim.qmsg
..........\..\shuzizhong.sim.rdb
..........\..\shuzizhong.sld_design_entry.sci
..........\..\shuzizhong.sld_design_entry_dsc.sci
..........\..\shuzizhong.syn_hier_info
..........\..\shuzizhong_cmp.qrpt
..........\..\sign_div_unsign_khg.tdf
..........\fangzhen.vwf
..........\shuzizhong.bsf
..........\shuzizhong.done
..........\shuzizhong.flow.rpt
..........\shuzizhong.map.eqn
..........\shuzizhong.map.rpt
..........\shuzizhong.map.summary
..........\shuzizhong.qpf
..........\shuzizhong.qsf
..........\shuzizhong.qws
..........\shuzizhong.sim.rpt
..........\shuzizhong.v
..........\db
shuzizhong

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