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Uart_to_bus

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-12-29
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Introduction - If you have any usage issues, please Google them yourself
The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode commands are designed to be used with a hyper terminal software and enable easy access to the internal bus. Binary mode commands are more efficient and also support buffered read & write operations with or without automatic address increment.
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Uart_to_bus
...........\uart2bus
...........\........\branches
...........\........\tags
...........\........\trunk
...........\........\.....\doc
...........\........\.....\...\UART to Bus Core Specifications.pdf
...........\........\.....\scilab
...........\........\.....\......\calc_baud_gen.sce
...........\........\.....\verilog
...........\........\.....\.......\bench
...........\........\.....\.......\.....\reg_file_model.v
...........\........\.....\.......\.....\tb_bin_uart2bus_top.v
...........\........\.....\.......\.....\tb_txt_uart2bus_top.v
...........\........\.....\.......\.....\tb_uart2bus_top.v
...........\........\.....\.......\.....\timescale.v
...........\........\.....\.......\.....\uart_tasks.v
...........\........\.....\.......\rtl
...........\........\.....\.......\...\baud_gen.v
...........\........\.....\.......\...\uart2bus_top.v
...........\........\.....\.......\...\uart_parser.v
...........\........\.....\.......\...\uart_rx.v
...........\........\.....\.......\...\uart_top.v
...........\........\.....\.......\...\uart_tx.v
...........\........\.....\.......\sim
...........\........\.....\.......\...\icarus
...........\........\.....\.......\...\......\block_bin.cfg
...........\........\.....\.......\...\......\block_txt.cfg
...........\........\.....\.......\...\......\compile_bin.bat
...........\........\.....\.......\...\......\compile_txt.bat
...........\........\.....\.......\...\......\gtk.bat
...........\........\.....\.......\...\......\run.bat
...........\........\.....\.......\...\......\test.bin
...........\........\.....\.......\...\......\test.txt
...........\........\.....\.......\syn
...........\........\.....\.......\...\altera
...........\........\.....\.......\...\......\uart2bus.qpf
...........\........\.....\.......\...\......\uart2bus.qws
...........\........\.....\.......\...\......\uart2bus_top.qsf
...........\........\.....\.......\...\xilinx
...........\........\.....\.......\...\......\uart2bus.xise
...........\........\.....\vhdl
...........\........\.....\....\bench
...........\........\.....\....\.....\helpers
...........\........\.....\....\.....\.......\helpers_pkg.vhd
...........\........\.....\....\.....\.......\regFileModel.vhd
...........\........\.....\....\.....\uart2BusTop_bin_tb.vhd
...........\........\.....\....\.....\uart2BusTop_txt_tb.vhd
...........\........\.....\....\rtl
...........\........\.....\....\...\baudGen.vhd
...........\........\.....\....\...\uart2BusTop.vhd
...........\........\.....\....\...\uart2BusTop_pkg.vhd
...........\........\.....\....\...\uartParser.vhd
...........\........\.....\....\...\uartRx.vhd
...........\........\.....\....\...\uartTop.vhd
...........\........\.....\....\...\uartTx.vhd
...........\........\.....\....\sim
...........\........\.....\....\...\modelsim
...........\........\.....\....\...\........\uart2bus_bin_sim.bat
...........\........\.....\....\...\........\uart2bus_bin_sim.tcl
...........\........\.....\....\...\........\uart2bus_txt_sim.bat
...........\........\.....\....\...\........\uart2bus_txt_sim.tcl
...........\........\.....\....\...\........\wave_uart2bus_bin.do
...........\........\.....\....\...\........\wave_uart2bus_txt.do
...........\........\.....\....\...\test.bin
...........\........\.....\....\...\test.txt
...........\........\.....\....\syn
...........\........\.....\....\...\xilinx
...........\........\.....\....\...\......\uart2bus.xise
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