Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed

hdb3_v2.2\change_out.v
.........\db\hdb3.amm.cdb
.........\..\hdb3.asm.qmsg
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.........\..\hdb3.asm_labs.ddb
.........\..\hdb3.cbx.xml
.........\..\hdb3.cmp.bpm
.........\..\hdb3.cmp.cdb
.........\..\hdb3.cmp.hdb
.........\..\hdb3.cmp.kpt
.........\..\hdb3.cmp.logdb
.........\..\hdb3.cmp.rdb
.........\..\hdb3.cmp0.ddb
.........\..\hdb3.cmp1.ddb
.........\..\hdb3.cmp2.ddb
.........\..\hdb3.cmp_merge.kpt
.........\..\hdb3.db_info
.........\..\hdb3.eda.qmsg
.........\..\hdb3.fit.qmsg
.........\..\hdb3.hier_info
.........\..\hdb3.hif
.........\..\hdb3.idb.cdb
.........\..\hdb3.lpc.html
.........\..\hdb3.lpc.rdb
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.........\..\hdb3.map.bpm
.........\..\hdb3.map.cdb
.........\..\hdb3.map.hdb
.........\..\hdb3.map.kpt
.........\..\hdb3.map.logdb
.........\..\hdb3.map.qmsg
.........\..\hdb3.map_bb.cdb
.........\..\hdb3.map_bb.hdb
.........\..\hdb3.map_bb.logdb
.........\..\hdb3.pre_map.cdb
.........\..\hdb3.pre_map.hdb
.........\..\hdb3.rpp.qmsg
.........\..\hdb3.rtlv.hdb
.........\..\hdb3.rtlv_sg.cdb
.........\..\hdb3.rtlv_sg_swap.cdb
.........\..\hdb3.sgate.rvd
.........\..\hdb3.sgate_sm.rvd
.........\..\hdb3.sgdiff.cdb
.........\..\hdb3.sgdiff.hdb
.........\..\hdb3.sld_design_entry.sci
.........\..\hdb3.sld_design_entry_dsc.sci
.........\..\hdb3.smart_action.txt
.........\..\hdb3.sta.qmsg
.........\..\hdb3.sta.rdb
.........\..\hdb3.sta_cmp.8_slow.tdb
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.........\..\hdb3.tmw_info
.........\..\logic_util_heursitic.dat
.........\..\prev_cmp_hdb3.qmsg
.........\d_module.v
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.........\hdb3.asm.rpt
.........\hdb3.done
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.........\hdb3.map.smsg
.........\hdb3.map.summary
.........\hdb3.pin
.........\hdb3.pof
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.........\hdb3.qsf
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.........\hdb3.sta.rpt
.........\hdb3.sta.summary
.........\hdb3.v
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.........\hdb3_create.v
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.........\hdb3_create_t.v
.........\hdb3_create_t.v.bak
.........\hdb3_nativelink_simulation.rpt
.........\incremental_db\compiled_partitions\hdb3.db_info
.........\..............\...................\hdb3.root_partition.cmp.cbp
.........\..............\...................\hdb3.root_partition.cmp.cdb
.........\..............\...................\hdb3.root_partition.cmp.dfp
.........\..............\...................\hdb3.root_partition.cmp.hdb
.........\..............\...................\hdb3.root_partition.cmp.kpt
.........\..............\...................\hdb3.root_partition.cmp.logdb
.........\..............\...................\hdb3.root_partition.cmp.rcfdb
.........\..............\...................\hdb3.root_partition.cmp.re.rcfdb
.........\..............\...................\hdb3.root_partition.map.cbp
.........\..............\...................\hdb3.root_partition.map.cdb
.........\..............\...................\hdb3.root_partition.map.dpi
.........\..............\...................\hdb3.root_partition.map.hdb
.........\..............\...................\hdb3.root_partition.map.kpt
.........\..............\README
.........\simulation\modelsim\gate_work\hdb3_create\verilog.prw
.........\..........\........\.........\...........\verilog.psm
.........\..........\........\.........\...........\_primary.dat
.........\..........\........\.........\...........\_primary.dbs

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