In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay.We also show a comparison of tolerance against noise and process variation between the different designs. The two proposed designs are found to be as robust as an existing D-flipflop both commercial standard cell libraries. Meanwhile, they are 33 and 25 faster in 65nm post-layout and 25 and 22 faster in 28nm post-layout compared to a commercial D-flipflop.

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