ddr3 controller based on Verilog HDL，used in lattice ECP3 serial FPGA

ddr3_demo_verilog
.................\core
.................\....\ddr3core.lpc
.................\resource
.................\........\16bit_support
.................\........\.............\core
.................\........\.............\....\ddr3core.lpc
.................\........\.............\lpf
.................\........\.............\...\ecp3_ddr3.lpf
.................\........\32bit_support
.................\........\.............\core
.................\........\.............\....\ddr3core.lpc
.................\........\.............\lpf
.................\........\.............\...\ecp3_ddr3.lpf
.................\........\64bit_dual_rank
.................\........\...............\core
.................\........\...............\....\ddr3core.lpc
.................\........\...............\lpf
.................\........\...............\...\ecp3_ddr3.lpf
.................\........\bitstream
.................\........\.........\64bit
.................\........\.........\.....\ecp3_ddr3_impl1.bit
.................\........\doc
.................\........\...\readme.txt
.................\user_logic
.................\..........\par
.................\..........\...\diamond
.................\..........\...\.......\.run_manager.ini
.................\..........\...\.......\ecp3_ddr3.ldf
.................\..........\...\.......\ecp3_ddr3.lpf
.................\..........\...\.......\ecp3_ddr3.pty
.................\..........\...\.......\ecp3_ddr3.tpf
.................\..........\...\.......\impl1
.................\..........\...\.......\.....\.build_status
.................\..........\...\.......\.....\ecp3_ddr3_impl1_summary.html
.................\..........\...\.......\post_route_trace.prf
.................\..........\...\.......\reportview.xml
.................\..........\...\.......\Strategy1.sty
.................\..........\sim
.................\..........\...\aldec
.................\..........\...\.....\ddr3_ecp3_demo.do
.................\..........\...\.....\wave.do
.................\..........\...\modelsim
.................\..........\...\........\ddr3_ecp3_demo.do
.................\..........\...\........\wave.do
.................\..........\src
.................\..........\...\data_gen_chk.v
.................\..........\...\ddr3_test_params.v
.................\..........\...\ddr3_test_top.v
.................\..........\...\ddr_ulogic.v
.................\..........\...\debounce.v
.................\..........\...\lfsr128.v
.................\..........\...\lfsr32.v
.................\..........\testbench
.................\..........\.........\ddr3_test_top_tb.v

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．