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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-05-18
  • Size : 152kb
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  • Author :常****
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Mechanical switch debounce circuit, removing problems caused due to jitter
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..........\cmp_state.ini
..........\db
..........\..\qudou.asm.qmsg
..........\..\qudou.cbx.xml
..........\..\qudou.cmp.cdb
..........\..\qudou.cmp.hdb
..........\..\qudou.cmp.rdb
..........\..\qudou.cmp.tdb
..........\..\qudou.cmp0.ddb
..........\..\qudou.db_info
..........\..\qudou.eco.cdb
..........\..\qudou.eds_overflow
..........\..\qudou.fit.qmsg
..........\..\qudou.hier_info
..........\..\qudou.hif
..........\..\qudou.map.cdb
..........\..\qudou.map.hdb
..........\..\qudou.map.qmsg
..........\..\qudou.pre_map.cdb
..........\..\qudou.pre_map.hdb
..........\..\qudou.psp
..........\..\qudou.rtlv.hdb
..........\..\qudou.rtlv_sg.cdb
..........\..\qudou.rtlv_sg_swap.cdb
..........\..\qudou.sgdiff.cdb
..........\..\qudou.sgdiff.hdb
..........\..\qudou.signalprobe.cdb
..........\..\qudou.sim.hdb
..........\..\qudou.sim.qmsg
..........\..\qudou.sim.rdb
..........\..\qudou.sim.vwf
..........\..\qudou.sld_design_entry.sci
..........\..\qudou.sld_design_entry_dsc.sci
..........\..\qudou.syn_hier_info
..........\..\qudou.tan.qmsg
..........\..\qudou_cmp.qrpt
..........\..\qudou_sim.qrpt
..........\qudou.asm.rpt
..........\qudou.bsf
..........\qudou.done
..........\qudou.fit.eqn
..........\qudou.fit.rpt
..........\qudou.fit.summary
..........\qudou.flow.rpt
..........\qudou.map.eqn
..........\qudou.map.rpt
..........\qudou.map.summary
..........\qudou.pin
..........\qudou.pof
..........\qudou.qpf
..........\qudou.qsf
..........\qudou.qws
..........\qudou.sim.rpt
..........\qudou.sof
..........\qudou.tan.rpt
..........\qudou.tan.summary
..........\qudou.vhd
..........\qudou.vwf
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