Introduction - If you have any usage issues, please Google them yourself
74HC595 is a silicon CMOS device structure, compatible with low-voltage TTL circuits, to comply with JEDEC standards. 74HC595 is an 8-bit shift register and a memory, tri-state output. Shift register and the memory clock, respectively. At the rising edge SHcp (shift register clock input) is input to the shift register at the rising edge STcp (memory clock input) is input to storage register. If the two clocks together, the shift register is always earlier than the storage register a pulse. There is a serial shift register shift input (Ds), and a serial output (Q7 ), and a low-level asynchronous reset, there is a parallel storage register of eight, with three-state bus output, when when OE is enabled (low), the data storage register is output to the bus.