Simple operation steps using the ModelSim timing simulation for Altera design

timing_sim
..........\work
..........\....\altcdr_rx
..........\....\altcdr_tx
..........\....\.........\verilog.asm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\altclklock
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\altddio_bidir
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\altddio_in
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\altddio_out
..........\....\...........\verilog.asm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\altdpram
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\altfp_mult
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\altlvds_rx
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\altlvds_tx
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\altmult_accum
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\altmult_add
..........\....\...........\verilog.asm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\altpll
..........\....\......\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\altqpram
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\altshift_taps
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\altsqrt
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\altsyncram
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\alt_exc_dpram
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\alt_exc_upcore
..........\....\..............\verilog.asm
..........\....\..............\_primary.dat
..........\....\..............\_primary.vhd
..........\....\and1
..........\....\and16
..........\....\.....\verilog.asm
..........\....\.....\_primary.dat
..........\....\.....\_primary.vhd
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\arm_m_cntr
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\arm_n_cntr
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\arm_scale_cntr
..........\....\..............\verilog.asm
..........\....\..............\_primary.dat
..........\....\..............\_primary.vhd
..........\....\a_graycounter
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\b17mux21

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