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Verilog设计与验证\Example-4-17\asyn_rst\asyn_rst.prd
.................\............\........\asyn_rst.prj
.................\............\........\asyn_rst.v
.................\............\........\rev_1\asyn_rst.edn
.................\............\........\.....\asyn_rst.fse
.................\............\........\.....\asyn_rst.prf
.................\............\........\.....\asyn_rst.srm
.................\............\........\.....\asyn_rst.srr
.................\............\........\.....\asyn_rst.srs
.................\............\........\.....\asyn_rst.tlg
.................\............\........\.....\AutoConstraint_asyn_rst.sdc
.................\............\........\.....\generic.fse
.................\............\........\.....\generic.srd
.................\............\........\.....\syntmp\asyn_rst.msg
.................\............\........\.....\......\asyn_rst.plg
.................\............\........_syn_release\asyn_rst_syn_release.v
.................\............\syn_rst\rev_2\AutoConstraint_syn_rst.sdc
.................\............\.......\.....\generic.fse
.................\............\.......\.....\generic.srd
.................\............\.......\.....\syntmp\syn_rst.msg
.................\............\.......\.....\......\syn_rst.plg
.................\............\.......\.....\syn_rst.edn
.................\............\.......\.....\syn_rst.fse
.................\............\.......\.....\syn_rst.prf
.................\............\.......\.....\syn_rst.srm
.................\............\.......\.....\syn_rst.srr
.................\............\.......\.....\syn_rst.srs
.................\............\.......\.....\syn_rst.tlg
.................\............\.......\syntmp.msg
.................\............\.......\syn_rst.prd
.................\............\.......\syn_rst.prj
.................\............\.......\syn_rst.v
.................\............\示例说明.doc
.................\..........20\case\case1.v
.................\............\....\PrecisionRTL\case.psp
.................\............\....\............\...._impl_1\case1.edf
.................\............\....\............\...........\case1.prf
.................\............\....\............\...........\case1.xdb
.................\............\....\............\...........\case1_area.rep
.................\............\....\............\...........\case1_con_rep.sdc
.................\............\....\............\...........\case1_rtl.ixdb
.................\............\....\............\...........\case1_tech_con_rep.sdc
.................\............\....\............\...........\case1_timing.rep
.................\............\....\............\...........\case_impl_1.psi
.................\............\....\............\...........\hdlAnalyze_verilogfile
.................\............\....\............\...........\precision.log
.................\............\....\............\...........\precision_rtl.sdc
.................\............\....\............\...........\precision_tech.sdc
.................\............\....\............\...........\rtlc.out\.rtlc_compile
.................\............\....\............\...........\........\.top
.................\............\....\............\...........\........\autotop.conf
.................\............\....\............\...........\........\depend\TOPMODULE.list
.................\............\....\............\...........\........\INCR\emptymod.list
.................\............\....\............\...........\........\....\hier.list
.................\............\....\............\...........\........\....\incr_driver.log
.................\............\....\............\...........\........\....\incr_rtlc.log
.................\............\....\............\...........\........\legalmodmap.db
.................\............\....\............\...........\........\rtlc.args
.................\............\....\............\...........\........\rtlc_args1.file
.................\............\....\............\...........\........\vmw.mem_contents
.................\............\....\..

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