Based on the FPGA implementation of DDR2_SDRAM Verilog code, more practical, proven by simulation.

DDR2_VERILOG\trunk\Buttons_VHDL.vhd
............\.....\Clock_VHDL.vhd
............\.....\DDR2_Control_VHDL.vhd
............\.....\DDR2_liesmich.txt
............\.....\DDR2_readme.txt
............\.....\DDR2_Read_VHDL.vhd
............\.....\DDR2_Write_VHDL.vhd
............\.....\impact.xsl
............\.....\impact_impact.xwbt
............\.....\.pcore_dir\DDR2_Ram_Core\user_design\par\UB_DDR2_64bit_UCF.ucf
............\.....\..........\.............\...........\rtl\DDR2_Ram_Core.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_cal_ctl.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_cal_top.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_clk_dcm.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_controller_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_controller_iobs_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_data_path_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_data_path_iobs_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_data_read_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_data_read_controller_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_data_write_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_dqs_delay_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_fifo_0_wr_en_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_fifo_1_wr_en_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_infrastructure.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_infrastructure_iobs_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_infrastructure_top.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_iobs_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_parameters_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_ram8d_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_rd_gray_cntr.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_s3_dm_iob.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_s3_dqs_iob.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_s3_dq_iob.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_tap_dly.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_top_0.vhd
............\.....\..........\.............\...........\...\DDR2_Ram_Core_wr_gray_cntr.vhd
............\.....\.seconfig\Prj_12_DDR2.projectmgr
............\.....\.........\Top_Modul_VHDL.xreport
............\.....\MIG_Settings\b01_part.JPG
............\.....\............\b02_generation.JPG
............\.....\............\b03_advanced.JPG
............\.....\............\b04_mig_361.JPG
............\.....\............\m01_customize.JPG
............\.....\............\m02_Create_Design.JPG
............\.....\............\m03_FPGAs.JPG
............\.....\............\m04_Memory.JPG
............\.....\............\m05_Controller.JPG
............\.....\............\m06_Options.JPG
............\.....\............\m07_Options2.JPG
............\.....\............\m08_Pins.JPG
............\.....\............\m09_Bank.JPG
............\.....\............\m10_Summary.JPG
............\.....\............\m11_License.JPG
............\.....\............\m12_PCB.JPG
............\.....\............\m13_Design.JPG
............\.....\............\m14_Coregen_Readme.JPG
............\.....\Prj12_Impact.ipf
............\.....\Prj_12_DDR2.gise
............\.....\Prj_12_DDR2.xise
............\.....\Top_Modul_VHDL.vhd
............\.....\Top_Modul_VHDL_bitgen.xwbt
............\.....\Top_Modul_VHDL_guide.ncd
............\.....\Top_Modul_VHDL_sum

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