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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-06-28
  • Size : 421kb
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  • Author :c*****
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Introduction - If you have any usage issues, please Google them yourself
this system develop a clock that can display on the screen
Packet file list
(Preview for download)


读I2C(自己写的)\db\logic_util_heursitic.dat
.................\..\prev_cmp_UP3_CLOCK.asm.qmsg
.................\..\prev_cmp_UP3_CLOCK.fit.qmsg
.................\..\prev_cmp_UP3_CLOCK.map.qmsg
.................\..\prev_cmp_UP3_CLOCK.qmsg
.................\..\prev_cmp_UP3_CLOCK.tan.qmsg
.................\..\UP3_CLOCK.ace_cmp.cdb
.................\..\UP3_CLOCK.ace_cmp.hdb
.................\..\UP3_CLOCK.asm.qmsg
.................\..\UP3_CLOCK.asm.rdb
.................\..\UP3_CLOCK.cbx.xml
.................\..\UP3_CLOCK.cmp.cdb
.................\..\UP3_CLOCK.cmp.hdb
.................\..\UP3_CLOCK.cmp.kpt
.................\..\UP3_CLOCK.cmp.logdb
.................\..\UP3_CLOCK.cmp.rdb
.................\..\UP3_CLOCK.cmp.tdb
.................\..\UP3_CLOCK.cmp0.ddb
.................\..\UP3_CLOCK.db_info
.................\..\UP3_CLOCK.eco.cdb
.................\..\UP3_CLOCK.fit.qmsg
.................\..\UP3_CLOCK.hier_info
.................\..\UP3_CLOCK.hif
.................\..\UP3_CLOCK.lpc.html
.................\..\UP3_CLOCK.lpc.rdb
.................\..\UP3_CLOCK.lpc.txt
.................\..\UP3_CLOCK.map.cdb
.................\..\UP3_CLOCK.map.hdb
.................\..\UP3_CLOCK.map.logdb
.................\..\UP3_CLOCK.map.qmsg
.................\..\UP3_CLOCK.pre_map.cdb
.................\..\UP3_CLOCK.pre_map.hdb
.................\..\UP3_CLOCK.rpp.qmsg
.................\..\UP3_CLOCK.rtlv.hdb
.................\..\UP3_CLOCK.rtlv_sg.cdb
.................\..\UP3_CLOCK.rtlv_sg_swap.cdb
.................\..\UP3_CLOCK.sgate.rvd
.................\..\UP3_CLOCK.sgate_sm.rvd
.................\..\UP3_CLOCK.sgdiff.cdb
.................\..\UP3_CLOCK.sgdiff.hdb
.................\..\UP3_CLOCK.sim.cvwf
.................\..\UP3_CLOCK.sim.hdb
.................\..\UP3_CLOCK.sim.qmsg
.................\..\UP3_CLOCK.sim.rdb
.................\..\UP3_CLOCK.sld_design_entry.sci
.................\..\UP3_CLOCK.sld_design_entry_dsc.sci
.................\..\UP3_CLOCK.smart_action.txt
.................\..\UP3_CLOCK.smp_dump.txt
.................\..\UP3_CLOCK.syn_hier_info
.................\..\UP3_CLOCK.tan.qmsg
.................\..\UP3_CLOCK.tis_db_list.ddb
.................\..\UP3_CLOCK.tmw_info
.................\..\wed.wsf
.................\incremental_db\compiled_partitions\UP3_CLOCK.root_partition.map.kpt
.................\..............\README
.................\UP3_CLOCK.asm.rpt
.................\UP3_CLOCK.done
.................\UP3_CLOCK.fit.rpt
.................\UP3_CLOCK.fit.smsg
.................\UP3_CLOCK.fit.summary
.................\UP3_CLOCK.flow.rpt
.................\UP3_CLOCK.map.rpt
.................\UP3_CLOCK.map.summary
.................\UP3_CLOCK.pin
.................\UP3_CLOCK.pof
.................\UP3_CLOCK.qpf
.................\UP3_CLOCK.qsf
.................\UP3_CLOCK.qws
.................\UP3_CLOCK.sim.rpt
.................\UP3_CLOCK.sof
.................\UP3_CLOCK.tan.rpt
.................\UP3_CLOCK.tan.summary
.................\UP3_CLOCK.vhd
.................\UP3_CLOCK.vhd.bak
.................\UP3_CLOCK_assignment_defaults.qdf
.................\incremental_db\compiled_partitions
.................\db
.................\incremental_db
读I2C(自己写的)
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