8 bit ternary multiplier using mux technique. Results of FPGA implementation.

ternary_report\ter3.v
..............\ternary3_pwr.txt
..............\ternary3_synthesis_report.txt
..............\ternary8_pwr_report.txt
..............\ternary8_synthesis_report.txt
..............\ternary_8.v
ternary_report

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