VHDL counter odd mode duty cycle 0.5

state10
.......\db
.......\..\add_sub_3rh.tdf
.......\..\add_sub_5rh.tdf
.......\..\add_sub_inh.tdf
.......\..\mux_1hc.tdf
.......\..\mux_3ec.tdf
.......\..\prev_cmp_state10.qmsg
.......\..\state10.cbx.xml
.......\..\state10.db_info
.......\..\state10.eco.cdb
.......\..\state10.eds_overflow
.......\..\state10.fnsim.cdb
.......\..\state10.fnsim.hdb
.......\..\state10.fnsim.qmsg
.......\..\state10.hier_info
.......\..\state10.lpc.html
.......\..\state10.lpc.rdb
.......\..\state10.lpc.txt
.......\..\state10.sim.cvwf
.......\..\state10.sim.hdb
.......\..\state10.sim.qmsg
.......\..\state10.sim.rdb
.......\..\state10.sim.vwf
.......\..\state10.simfam
.......\..\state10.sld_design_entry.sci
.......\..\state10.sld_design_entry_dsc.sci
.......\..\state10.smart_action.txt
.......\..\wed.wsf
.......\..\wed.zsf
.......\EDA43.doc
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\README
.......\state10.asm.rpt
.......\state10.done
.......\state10.fit.rpt
.......\state10.fit.smsg
.......\state10.fit.summary
.......\state10.flow.rpt
.......\state10.map.rpt
.......\state10.map.summary
.......\state10.pin
.......\state10.pof
.......\state10.qpf
.......\state10.qsf
.......\state10.qws
.......\state10.sim.rpt
.......\state10.sof
.......\state10.tan.rpt
.......\state10.tan.summary
.......\state10.tdf
.......\state10.vhd
.......\state10.vwf
.......\state10_assignment_defaults.qdf

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