Introduces an FPGA-based FIR filter circuit systems and high-precision A/D converter combined, the filter algorithm using multiplier-accumulator, and use X ilinx company XC3S500E of FPGA verification test, including the input sine wave filtering the signal for A/D conversion, filtering results displayed by the host computer.

fir18\.sopc_builder\filters.xml
.....\.............\preferences.xml
.....\Acc_Sub.v
.....\Acc_Sub.v.bak
.....\db\fir18.amm.cdb
.....\..\fir18.asm.qmsg
.....\..\fir18.asm.rdb
.....\..\fir18.asm_labs.ddb
.....\..\fir18.cbx.xml
.....\..\fir18.cmp.bpm
.....\..\fir18.cmp.cdb
.....\..\fir18.cmp.hdb
.....\..\fir18.cmp.kpt
.....\..\fir18.cmp.logdb
.....\..\fir18.cmp.rdb
.....\..\fir18.cmp0.ddb
.....\..\fir18.cmp1.ddb
.....\..\fir18.cmp_merge.kpt
.....\..\fir18.db_info
.....\..\fir18.eda.qmsg
.....\..\fir18.fit.qmsg
.....\..\fir18.hier_info
.....\..\fir18.hif
.....\..\fir18.idb.cdb
.....\..\fir18.lpc.html
.....\..\fir18.lpc.rdb
.....\..\fir18.lpc.txt
.....\..\fir18.map.bpm
.....\..\fir18.map.cdb
.....\..\fir18.map.hdb
.....\..\fir18.map.kpt
.....\..\fir18.map.logdb
.....\..\fir18.map.qmsg
.....\..\fir18.map_bb.cdb
.....\..\fir18.map_bb.hdb
.....\..\fir18.map_bb.logdb
.....\..\fir18.pre_map.cdb
.....\..\fir18.pre_map.hdb
.....\..\fir18.rtlv.hdb
.....\..\fir18.rtlv_sg.cdb
.....\..\fir18.rtlv_sg_swap.cdb
.....\..\fir18.sgdiff.cdb
.....\..\fir18.sgdiff.hdb
.....\..\fir18.sim_ori.vwf
.....\..\fir18.sld_design_entry.sci
.....\..\fir18.sld_design_entry_dsc.sci
.....\..\fir18.smart_action.txt
.....\..\fir18.sta.qmsg
.....\..\fir18.sta.rdb
.....\..\fir18.sta_cmp.6_slow.tdb
.....\..\fir18.syn_hier_info
.....\..\fir18.tis_db_list.ddb
.....\..\fir18.tmw_info
.....\..\fir18_global_asgn_op.abo
.....\..\logic_util_heursitic.dat
.....\..\prev_cmp_fir18.asm.qmsg
.....\..\prev_cmp_fir18.eda.qmsg
.....\..\prev_cmp_fir18.fit.qmsg
.....\..\prev_cmp_fir18.map.qmsg
.....\..\prev_cmp_fir18.qmsg
.....\..\prev_cmp_fir18.sim.qmsg
.....\..\prev_cmp_fir18.tan.qmsg
.....\..\wed.wsf
.....\enter.bsf
.....\enter.v
.....\enter.v.bak
.....\enter.vwf
.....\fir18.asm.rpt
.....\fir18.done
.....\fir18.eda.rpt
.....\fir18.fit.rpt
.....\fir18.fit.smsg
.....\fir18.fit.summary
.....\fir18.flow.rpt
.....\fir18.map.rpt
.....\fir18.map.smsg
.....\fir18.map.summary
.....\fir18.pin
.....\fir18.pof
.....\fir18.qpf
.....\fir18.qsf
.....\fir18.qws
.....\fir18.sim.rpt
.....\fir18.sof
.....\fir18.sta.rpt
.....\fir18.sta.summary
.....\fir18.tan.rpt
.....\fir18.tan.summary
.....\fir18.v.bak
.....\fir18_assignment_defaults.qdf
.....\fir18_nativelink_simulation.rpt
.....\Firfilter.v
.....\Firfilter.v.bak
.....\firfilter.vwf
.....\incremental_db\compiled_partitions\fir18.db_info
.....\..............\...................\fir18.root_partition.cmp.atm
.....\..............\...................\fir18.root_partition.cmp.cdb
.....\..............\...................\fir18.root_partition.cmp.dfp
.....\..............\...................\fir18.root_partition.cmp.hdb
.....\..............\...................\fir18.root_partition.cmp.hdbx

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．