FPGA-based implementation of a digital clock, as well as hardware emulation, you need to use quartusii_60_sp1_web_edition software.

clock
.....\ALERT.BSF
.....\ALERT.VHD
.....\CLOCK.ASM.RPT
.....\CLOCK.BDF
.....\CLOCK.DONE
.....\CLOCK.FIT.EQN
.....\CLOCK.FIT.RPT
.....\clock.fit.summary
.....\CLOCK.FLOW.RPT
.....\CLOCK.MAP.EQN
.....\CLOCK.MAP.RPT
.....\clock.map.summary
.....\CLOCK.PIN
.....\CLOCK.POF
.....\CLOCK.QPF
.....\CLOCK.QSF
.....\CLOCK.QWS
.....\CLOCK.SOF
.....\CLOCK.TAN.RPT
.....\CLOCK.TAN.SUMMARY
.....\clock_assignment_defaults.qdf
.....\CMP_STATE.INI
.....\DB
.....\..\add_sub_0ih.tdf
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.logdb
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.fit.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.logdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.pss
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\..\CLOCK_CMP.QRPT
.....\..\CLOCK_HIER_INFO
.....\..\CLOCK_SYN_HIER_INFO
.....\DELED.BSF
.....\DELED.VHD
.....\HOUR.BSF
.....\HOUR.VHD
.....\MINUTE.BSF
.....\MINUTE.VHD
.....\SECOND.BSF
.....\SECOND.VHD
.....\SELTIME.BSF
.....\SELTIME.VHD

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