Xilinx FPGA internal RAM usage experiments

bram\introduce.txt
....\project\Block_Ram\.untf
....\.......\.........\automake.log
....\.......\.........\Block_Ram.ise
....\.......\.........\Block_Ram.ise_ISE_Backup
....\.......\.........\core.tpl
....\.......\.........\nofirst.ngo
....\.......\.........\nofirst.v
....\.......\.........\nofirst.xco
....\.......\.........\nofirstip_test.v
....\.......\.........\nofirstip_test_v.fdo
....\.......\.........\nofirstip_test_v.ndo
....\.......\.........\nofirstip_test_v.udo
....\.......\.........\top_nofirst.bld
....\.......\.........\top_nofirst.cmd_log
....\.......\.........\top_nofirst.lso
....\.......\.........\top_nofirst.ngc
....\.......\.........\top_nofirst.ngd
....\.......\.........\top_nofirst.ngr
....\.......\.........\top_nofirst.prj
....\.......\.........\top_nofirst.stx
....\.......\.........\top_nofirst.syr
....\.......\.........\top_nofirst.v
....\.......\.........\top_nofirst.versim_xlate
....\.......\.........\top_nofirst.xlate_nlf
....\.......\.........\top_nofirst_summary.html
....\.......\.........\top_nofirst_translate.nlf
....\.......\.........\top_nofirst_translate.v
....\.......\.........\top_nofirst_vhdl.prj
....\.......\.........\top_write_first.v
....\.......\.........\transcript
....\.......\.........\work\glbl\verilog.asm
....\.......\.........\....\....\_primary.dat
....\.......\.........\....\....\_primary.vhd
....\.......\.........\....\nofirst\verilog.asm
....\.......\.........\....\.......\_primary.dat
....\.......\.........\....\.......\_primary.vhd
....\.......\.........\....\.......ip_test_v\verilog.asm
....\.......\.........\....\................\_primary.dat
....\.......\.........\....\................\_primary.vhd
....\.......\.........\....\top_nofirst\verilog.asm
....\.......\.........\....\...........\_primary.dat
....\.......\.........\....\...........\_primary.vhd
....\.......\.........\....\....write_first\verilog.asm
....\.......\.........\....\...............\_primary.dat
....\.......\.........\....\...............\_primary.vhd
....\.......\.........\....\writefirstip_test_v\verilog.asm
....\.......\.........\....\...................\_primary.dat
....\.......\.........\....\...................\_primary.vhd
....\.......\.........\....\....._first\verilog.asm
....\.......\.........\....\...........\_primary.dat
....\.......\.........\....\...........\_primary.vhd
....\.......\.........\....\_info
....\.......\.........\writefirstip_test.v
....\.......\.........\writefirstip_test_v.fdo
....\.......\.........\writefirstip_test_v.udo
....\.......\.........\write_first.ngo
....\.......\.........\write_first.v
....\.......\.........\write_first.xco
....\.......\.........\xst\work\hdllib.ref
....\.......\.........\...\....\vlg3B\top__nofirst.bin
....\.......\.........\...\....\...79\nofirst.bin
....\.......\.........\_ngo\netlist.lst
....\.......\.........\__ISE_repository_Block_Ram.ise_.lock
....\.......\.........\..projnav\block_ram.gfl
....\.......\.........\.........\Block_Ram_flowplus.gfl
....\.......\.........\.........\ednTOngd_tcl.rsp
....\.......\.........\.........\runXst_tcl.rsp
....\.......\.........\.........\sumrpt_tcl.rsp
....\.......\.........\.........\top_nofirst.xst
....\.......\.........\__projnav.log
....\.......\.........\xst\dump.xst\top_nofirst.prj\ngx\notopt
....\.......\.........\...\........\...............\...\opt
....\.......\.........\...\........\...............\ngx
....\.......\.........\...\........\top_nofirst.prj
....\.......\.........\...\work\vlg3B
....\.......\.........\...\....\vlg79
....\.......\.........\work\glbl
....\.......\.........\....\nofirst
....\.......\.........\....\nofirstip_test_v
....\.......\.........\....\top_nofirst
....\.......\.........\....\top_write_first
....\.......\.........\....\writefirstip_test_v
....\.......\.........\....\write_first
....\.......\.........\xst\dump.xst
....\.......\.........\...\work
....\.......\.........\work
....\.......\.........\xst
....\.......\.........\_ngo
....\.......\.........\_xmsgs
....\.......\.........\__projnav
....\.......\Block_Ram
....\project
bram

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