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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-05-19
  • Size : 14kb
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  • Author :徐***
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Introduction - If you have any usage issues, please Google them yourself
Run a first simulation with an alpha firing angle of 19 degrees. You should get a DC voltage level of 500 kV. Now, look inside Scope1. Compare the currents flowing into Bus B1 (Iabc_B1, axis 2) with those flowing into Bus B2 (Iabc_B2, axis 3). You can see that the harmonic filters almost eliminate the harmonics generated by the converter. If you use the FFT tool of the powergui, you will find that the harmonic filters reduce the THD of the current injected in the system from 9 to 0.7 . You can also perform other simulations with various values of alpha. Notice the impact on the DC level and on the generated harmonics.
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svc123.mdl
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