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syn_cnter_4_ok

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-05-19
  • Size : 159kb
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  • Author :流****
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Introduction - If you have any usage issues, please Google them yourself
FPGA application examples, and a brief introduction to the process and the coding process calculator design.
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syn_cnter_4_ok_四位计数器
.........................\db
.........................\..\syn_cnter_4.asm.qmsg
.........................\..\syn_cnter_4.asm_labs.ddb
.........................\..\syn_cnter_4.cbx.xml
.........................\..\syn_cnter_4.cmp.cdb
.........................\..\syn_cnter_4.cmp.hdb
.........................\..\syn_cnter_4.cmp.kpt
.........................\..\syn_cnter_4.cmp.logdb
.........................\..\syn_cnter_4.cmp.rdb
.........................\..\syn_cnter_4.cmp.tdb
.........................\..\syn_cnter_4.cmp0.ddb
.........................\..\syn_cnter_4.dbp
.........................\..\syn_cnter_4.db_info
.........................\..\syn_cnter_4.eco.cdb
.........................\..\syn_cnter_4.eds_overflow
.........................\..\syn_cnter_4.fit.qmsg
.........................\..\syn_cnter_4.hier_info
.........................\..\syn_cnter_4.hif
.........................\..\syn_cnter_4.map.cdb
.........................\..\syn_cnter_4.map.hdb
.........................\..\syn_cnter_4.map.logdb
.........................\..\syn_cnter_4.map.qmsg
.........................\..\syn_cnter_4.pre_map.cdb
.........................\..\syn_cnter_4.pre_map.hdb
.........................\..\syn_cnter_4.psp
.........................\..\syn_cnter_4.rtlv.hdb
.........................\..\syn_cnter_4.rtlv_sg.cdb
.........................\..\syn_cnter_4.rtlv_sg_swap.cdb
.........................\..\syn_cnter_4.sgdiff.cdb
.........................\..\syn_cnter_4.sgdiff.hdb
.........................\..\syn_cnter_4.signalprobe.cdb
.........................\..\syn_cnter_4.sim.hdb
.........................\..\syn_cnter_4.sim.qmsg
.........................\..\syn_cnter_4.sim.rdb
.........................\..\syn_cnter_4.sim_ori.vwf
.........................\..\syn_cnter_4.sld_design_entry.sci
.........................\..\syn_cnter_4.sld_design_entry_dsc.sci
.........................\..\syn_cnter_4.syn_hier_info
.........................\..\syn_cnter_4.tan.qmsg
.........................\..\wed.zsf
.........................\syn_cnter_4.asm.rpt
.........................\syn_cnter_4.done
.........................\syn_cnter_4.fit.rpt
.........................\syn_cnter_4.fit.smsg
.........................\syn_cnter_4.fit.summary
.........................\syn_cnter_4.flow.rpt
.........................\syn_cnter_4.map.rpt
.........................\syn_cnter_4.map.summary
.........................\syn_cnter_4.pin
.........................\syn_cnter_4.pof
.........................\syn_cnter_4.qpf
.........................\syn_cnter_4.qsf
.........................\syn_cnter_4.qws
.........................\syn_cnter_4.sim.rpt
.........................\syn_cnter_4.tan.rpt
.........................\syn_cnter_4.tan.summary
.........................\syn_cnter_4.vhd
.........................\syn_cnter_4.vwf
.........................\syn_cnter_4程序逐行解释.doc
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