Synchronous clear reversible counter with clock divider Verilog HDL language

同步清零的可逆计数器
....................\clk_div.bsf
....................\clk_div.v
....................\counter.bsf
....................\counter.v
....................\db
....................\..\design.asm.qmsg
....................\..\design.asm_labs.ddb
....................\..\design.cbx.xml
....................\..\design.cmp.cdb
....................\..\design.cmp.hdb
....................\..\design.cmp.logdb
....................\..\design.cmp.rdb
....................\..\design.cmp.tdb
....................\..\design.cmp0.ddb
....................\..\design.cmp2.ddb
....................\..\design.db_info
....................\..\design.eco.cdb
....................\..\design.fit.qmsg
....................\..\design.hier_info
....................\..\design.hif
....................\..\design.map.cdb
....................\..\design.map.hdb
....................\..\design.map.logdb
....................\..\design.map.qmsg
....................\..\design.pre_map.cdb
....................\..\design.pre_map.hdb
....................\..\design.rtlv.hdb
....................\..\design.rtlv_sg.cdb
....................\..\design.rtlv_sg_swap.cdb
....................\..\design.sgdiff.cdb
....................\..\design.sgdiff.hdb
....................\..\design.signalprobe.cdb
....................\..\design.sim.vwf
....................\..\design.sld_design_entry.sci
....................\..\design.sld_design_entry_dsc.sci
....................\..\design.syn_hier_info
....................\..\design.tan.qmsg
....................\..\design.tis_db_list.ddb
....................\..\design.tmw_info
....................\..\wed.zsf
....................\design.asm.rpt
....................\design.bdf
....................\design.cdf
....................\design.done
....................\design.dpf
....................\design.fit.rpt
....................\design.fit.smsg
....................\design.fit.summary
....................\design.flow.rpt
....................\design.map.rpt
....................\design.map.smsg
....................\design.map.summary
....................\design.pin
....................\design.pof
....................\design.qpf
....................\design.qsf
....................\design.qws
....................\design.sim.rpt
....................\design.sim.vwf
....................\design.sof
....................\design.tan.rpt
....................\design.tan.summary
....................\design.vwf
....................\design_assignment_defaults.qdf

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