DDS can produce all types and frequency and various amplitude modulated signals, but also to ensure the continuous phase, so it is widely used, but there may be doubt as to control for beginners DDS, the program uses the FPGA to control the DDS, the timing correct successfully written to the DDS values.

DDS SU
......\DDSTest
......\.......\AA.bsf
......\.......\AA.v
......\.......\AA.v.bak
......\.......\bb1.bsf
......\.......\bb1.v
......\.......\bb1.v.bak
......\.......\clkdiv.bsf
......\.......\clkdiv.inc
......\.......\clkdiv.v
......\.......\clkdiv.v.bak
......\.......\clkdivRS.bsf
......\.......\clkdivRS.v
......\.......\clkdivRS.v.bak
......\.......\datacontr.bsf
......\.......\datacontr.v
......\.......\datacontr.v.bak
......\.......\datasou.mif
......\.......\datasource.mif
......\.......\db
......\.......\..\altsyncram_f991.tdf
......\.......\..\DDSTest.amm.cdb
......\.......\..\DDSTest.asm.qmsg
......\.......\..\DDSTest.asm.rdb
......\.......\..\DDSTest.asm_labs.ddb
......\.......\..\DDSTest.cbx.xml
......\.......\..\DDSTest.cmp.bpm
......\.......\..\DDSTest.cmp.cdb
......\.......\..\DDSTest.cmp.hdb
......\.......\..\DDSTest.cmp.kpt
......\.......\..\DDSTest.cmp.logdb
......\.......\..\DDSTest.cmp.rdb
......\.......\..\DDSTest.cmp_merge.kpt
......\.......\..\DDSTest.cycloneive_io_sim_cache.45um_ff_1200mv_n40c_fast.hsd
......\.......\..\DDSTest.cycloneive_io_sim_cache.45um_ii_1200mv_100c_slow.hsd
......\.......\..\DDSTest.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
......\.......\..\DDSTest.cycloneive_io_sim_cache.45um_ii_1200mv_n40c_slow.hsd
......\.......\..\DDSTest.db_info
......\.......\..\DDSTest.eda.qmsg
......\.......\..\DDSTest.fit.qmsg
......\.......\..\DDSTest.hier_info
......\.......\..\DDSTest.hif
......\.......\..\DDSTest.idb.cdb
......\.......\..\DDSTest.lpc.html
......\.......\..\DDSTest.lpc.rdb
......\.......\..\DDSTest.lpc.txt
......\.......\..\DDSTest.map.bpm
......\.......\..\DDSTest.map.cdb
......\.......\..\DDSTest.map.hdb
......\.......\..\DDSTest.map.kpt
......\.......\..\DDSTest.map.logdb
......\.......\..\DDSTest.map.qmsg
......\.......\..\DDSTest.map.rdb
......\.......\..\DDSTest.map_bb.cdb
......\.......\..\DDSTest.map_bb.hdb
......\.......\..\DDSTest.map_bb.logdb
......\.......\..\DDSTest.pre_map.cdb
......\.......\..\DDSTest.pre_map.hdb
......\.......\..\DDSTest.root_partition.map.reg_db.cdb
......\.......\..\DDSTest.routing.rdb
......\.......\..\DDSTest.rtlv.hdb
......\.......\..\DDSTest.rtlv_sg.cdb
......\.......\..\DDSTest.rtlv_sg_swap.cdb
......\.......\..\DDSTest.sgdiff.cdb
......\.......\..\DDSTest.sgdiff.hdb
......\.......\..\DDSTest.sld_design_entry.sci
......\.......\..\DDSTest.sld_design_entry_dsc.sci
......\.......\..\DDSTest.smart_action.txt
......\.......\..\DDSTest.sta.qmsg
......\.......\..\DDSTest.sta.rdb
......\.......\..\DDSTest.sta_cmp.7_slow_1200mv_100c.tdb
......\.......\..\DDSTest.syn_hier_info
......\.......\..\DDSTest.tiscmp.fastest_slow_1200mv_85c.ddb
......\.......\..\DDSTest.tiscmp.fastest_slow_1200mv_n40c.ddb
......\.......\..\DDSTest.tiscmp.fast_1200mv_n40c.ddb
......\.......\..\DDSTest.tiscmp.slow_1200mv_100c.ddb
......\.......\..\DDSTest.tiscmp.slow_1200mv_n40c.ddb
......\.......\..\DDSTest.tis_db_list.ddb
......\.......\..\DDSTest.tmw_info
......\.......\..\logic_util_heursitic.dat
......\.......\..\mypll_altpll.v
......\.......\..\pll2_altpll.v
......\.......\..\prev_cmp_DDSTest.qmsg
......\.......\DD.bsf
......\.......\DD.v
......\.......\DD.v.bak
......\.......\DDSTest.asm.rpt
......\.......\DDSTest.bdf
......\.......\DDSTest.cdf
......\.......\DDSTest.done
......\.......\DDSTest.eda.rpt
......\.......\DDSTest.fit.rpt
......\.......\DDSTest.fit.smsg
......\.......\DDSTest.fit.summary
......\.......\DDSTest.flow.rpt
......\.......\DDSTest.jdi
......\.......\DDSTest.map.rpt
......\.......\DDSTest.map.smsg
......\.......\DDSTest.map.summary

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