The FPGA implemented in the DSB AM modulation with Modelsim simulation, the actual test: the carrier frequency, and modulation signal frequency is adjustable.

DSB
...\Code
...\....\AM.v
...\....\AM_tb.v
...\....\AM_tb.v.bak
...\....\CarrierWave.v
...\....\ModulateWave.v
...\....\ModulateWave.v.bak
...\....\Mult_10bs.v
...\....\Mult_14BS.v
...\....\sin.mif
...\....\sin_rom_10b.v
...\Modelsim
...\........\DSB.mpf
...\........\sin.mif
...\........\sin.ver
...\........\vsim.wlf
...\........\work
...\........\....\@a@m
...\........\....\....\verilog.asm
...\........\....\....\verilog.rw
...\........\....\....\_primary.dat
...\........\....\....\_primary.dbs
...\........\....\....\_primary.vhd
...\........\....\@carrier@wave
...\........\....\.............\verilog.asm
...\........\....\.............\verilog.rw
...\........\....\.............\_primary.dat
...\........\....\.............\_primary.dbs
...\........\....\.............\_primary.vhd
...\........\....\@modulate@wave
...\........\....\..............\verilog.asm
...\........\....\..............\verilog.rw
...\........\....\..............\_primary.dat
...\........\....\..............\_primary.dbs
...\........\....\..............\_primary.vhd
...\........\....\@mult_10bs
...\........\....\..........\verilog.asm
...\........\....\..........\verilog.rw
...\........\....\..........\_primary.dat
...\........\....\..........\_primary.dbs
...\........\....\..........\_primary.vhd
...\........\....\@mult_14@b@s
...\........\....\............\verilog.asm
...\........\....\............\verilog.rw
...\........\....\............\_primary.dat
...\........\....\............\_primary.dbs
...\........\....\............\_primary.vhd
...\........\....\m_tb
...\........\....\....\verilog.asm
...\........\....\....\verilog.rw
...\........\....\....\_primary.dat
...\........\....\....\_primary.dbs
...\........\....\....\_primary.vhd
...\........\....\sin_rom_10b
...\........\....\...........\verilog.asm
...\........\....\...........\verilog.rw
...\........\....\...........\_primary.dat
...\........\....\...........\_primary.dbs
...\........\....\...........\_primary.vhd
...\........\....\_info
...\........\....\_temp
...\........\....\_vmake

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