MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247

MSK
...\Code
...\....\cos.mif
...\....\cos_romm10b.v
...\....\Fs_Gen.v
...\....\IQ_sin_cos.v
...\....\IQ_sin_cos_mod.v
...\....\IQ_sin_cos_mod.v.bak
...\....\m.v
...\....\MSK.v
...\....\MSK.v.bak
...\....\msk_tb.v
...\....\Muly_10bS.v
...\....\s2p.v
...\....\sin.mif
...\....\sin_rom_10b.v
...\Modelsim
...\........\cos.mif
...\........\cos.ver
...\........\Msk_Sim.cr.mti
...\........\Msk_Sim.mpf
...\........\sin.mif
...\........\sin.ver
...\........\vsim.wlf
...\........\work
...\........\....\@i@q_sin_cos
...\........\....\............\verilog.asm
...\........\....\............\verilog.rw
...\........\....\............\_primary.dat
...\........\....\............\_primary.dbs
...\........\....\............\_primary.vhd
...\........\....\@i@q_sin_cos_mod
...\........\....\................\verilog.asm
...\........\....\................\verilog.rw
...\........\....\................\_primary.dat
...\........\....\................\_primary.dbs
...\........\....\................\_primary.vhd
...\........\....\@m@s@k
...\........\....\......\verilog.asm
...\........\....\......\verilog.rw
...\........\....\......\_primary.dat
...\........\....\......\_primary.dbs
...\........\....\......\_primary.vhd
...\........\....\@m@s@k_tb
...\........\....\.........\verilog.asm
...\........\....\.........\verilog.rw
...\........\....\.........\_primary.dat
...\........\....\.........\_primary.dbs
...\........\....\.........\_primary.vhd
...\........\....\@muly_10b@s
...\........\....\...........\verilog.asm
...\........\....\...........\verilog.rw
...\........\....\...........\_primary.dat
...\........\....\...........\_primary.dbs
...\........\....\...........\_primary.vhd
...\........\....\cos_romm10b
...\........\....\...........\verilog.asm
...\........\....\...........\verilog.rw
...\........\....\...........\_primary.dat
...\........\....\...........\_primary.dbs
...\........\....\...........\_primary.vhd
...\........\....\fs_@gen
...\........\....\.......\verilog.asm
...\........\....\.......\verilog.rw
...\........\....\.......\_primary.dat
...\........\....\.......\_primary.dbs
...\........\....\.......\_primary.vhd
...\........\....\s2p
...\........\....\...\verilog.asm
...\........\....\...\verilog.rw
...\........\....\...\_primary.dat
...\........\....\...\_primary.dbs
...\........\....\...\_primary.vhd
...\........\....\sin_rom_10b
...\........\....\...........\verilog.asm
...\........\....\...........\verilog.rw
...\........\....\...........\_primary.dat
...\........\....\...........\_primary.dbs
...\........\....\...........\_primary.vhd
...\........\....\wsj
...\........\....\...\verilog.asm
...\........\....\...\verilog.rw
...\........\....\...\_primary.dat
...\........\....\...\_primary.dbs
...\........\....\...\_primary.vhd
...\........\....\_info
...\........\....\_temp
...\........\....\_vmake

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